Datasheet > M53D1G3232A-5BG

M53D1G3232A-5BG

更新时间： 2024-09-26 02:51:27

品牌	Logo	应用领域
晶豪 - ESMT		动态存储器双倍数据速率
页数	文件大小	规格书
48页	1365K
描述
8M x 32Bit x 4 Banks Mobile DDR SDRAM

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中文翻译

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数据手册

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M53D1G3232A-5BG 数据手册

ESMT

(Prliminary)

M53D1G3232A

Mobile DDR SDRAM

8M x 32Bit x 4 Banks

Mobile DDR SDRAM

Features

All inputs except data & DM are sampled at the rising

edge of the system clock(CLK)

DQS is edge-aligned with data for READ; center-aligned

with data for WRITE

Data mask (DM) for write masking only

V_DD/V_DDQ= 1.7V ~ 1.95V

Auto & Self refresh

JEDEC Standard

Internal pipelined double-data-rate architecture, two data

access per clock cycle

Bi-directional data strobe (DQS)

No DLL; CLK to DQS is not synchronized.

Differential clock inputs (CLK and CLK )

Four bank operation

CAS Latency : 2, 3

Burst Type : Sequential and Interleave

Burst Length : 2, 4, 8, 16

Special function support

7.8us refresh interval (64ms refresh period, 8K cycle)

LVCMOS-compatible inputs

PASR (Partial Array Self Refresh)

Internal TCSR (Temperature Compensated Self

Refresh)

DS (Drive Strength)

Deep Power Down (DPD) Mode

Status Read Register (SRR)

Ordering Information

Product ID

Max Freq.

200MHz

166MHz

133MHz

V_DD

Package

Comments

M53D1G3232A-5BG

M53D1G3232A-6BG

M53D1G3232A-7.5BG

1.8V

144 ball FBGA

Pb-free

Functional Block Diagram

CLK

Clock

Generator

CLK

Bank D

Bank C

Bank B

CKE

Row

Address

Buffer

Refresh

Counter

Mode Register &

Extended Mode

Bank A

DQS

Sense Amplifier

Column Decoder

Column

Address

Buffer

RAS

CAS

Refresh

Counter

Data Control Circuit

Elite Semiconductor Memory Technology Inc.

Publication Date : Apr. 2016

Revision : 0.1 1/48

12 3 4 5 6 7...48

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