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M53D128168A_1 PDF预览

M53D128168A_1

更新时间: 2024-09-26 05:46:55
品牌 Logo 应用领域
晶豪 - ESMT 动态存储器双倍数据速率
页数 文件大小 规格书
46页 1076K
描述
2M x 16 Bit x 4 Banks Mobile DDR SDRAM

M53D128168A_1 数据手册

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ESMT  
M53D128168A  
Operation Temperature Condition -40°C~85°C  
Mobile DDR SDRAM  
2M x 16 Bit x 4 Banks  
Mobile DDR SDRAM  
Features  
z
z
JEDEC Standard  
Internal pipelined double-data-rate architecture, two data  
access per clock cycle  
Bi-directional data strobe (DQS)  
No DLL; CLK to DQS is not synchronized.  
z
All inputs except data & DM are sampled at the rising  
edge of the system clock(CLK)  
Data I/O transitions on both edges of data strobe (DQS)  
DQS is edge-aligned with data for READ; center-aligned  
with data for WRITE  
z
z
z
z
z
z
z
z
z
z
Data mask (DM) for write masking only  
VDD/VDDQ = 1.7V ~ 1.9V  
Auto & Self refresh  
15.6us refresh interval (64ms refresh period, 4K cycle)  
1.8V LVCMOS-compatible inputs  
60 ball BGA package  
z
z
z
z
z
z
Differential clock inputs (CLK and CLK )  
Quad bank operation  
CAS Latency : 2, 3  
Burst Type : Sequential and Interleave  
Burst Length : 2, 4, 8  
Special function support  
-
-
PASR (Partial Array Self Refresh)  
Internal TCSR (Temperature Compensated Self  
Refresh)  
-
DS (Driver Strength)  
Ordering information :  
Part NO.  
MAX FREQ  
133MHz  
VDD  
PACKAGE  
8x13 mm  
BGA  
COMMENTS  
Pb-free  
M53D128168A -7.5BAIG  
M53D128168A -10BAIG  
1.8V  
100MHz  
Pb-free  
Functional Block Diagram  
CLK  
Clock  
Generator  
CLK  
Bank D  
Bank C  
Bank B  
CKE  
Row  
Address  
Address  
Buffer  
&
Refresh  
Counter  
Mode Register &  
Extended Mode  
Register  
Bank A  
DQS  
DM  
Sense Amplifier  
Column Decoder  
Column  
Address  
Buffer  
&
Refresh  
Counter  
CS  
RAS  
CAS  
WE  
Data Control Circuit  
DQ  
Elite Semiconductor Memory Technology Inc.  
Publication Date : Dec. 2008  
Revision : 1.0 1/46  

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