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M53D128168A-7.5BIG2E PDF预览

M53D128168A-7.5BIG2E

更新时间: 2024-11-13 19:52:15
品牌 Logo 应用领域
晶豪 - ESMT 动态存储器双倍数据速率内存集成电路
页数 文件大小 规格书
47页 1141K
描述
DDR DRAM, 8MX16, 6ns, CMOS, PBGA60, BGA-60

M53D128168A-7.5BIG2E 技术参数

生命周期:Contact Manufacturer包装说明:TFBGA,
Reach Compliance Code:unknown风险等级:5.7
访问模式:FOUR BANK PAGE BURST最长访问时间:6 ns
其他特性:AUTO/SELF REFRESHJESD-30 代码:R-PBGA-B60
长度:13 mm内存密度:134217728 bit
内存集成电路类型:DDR DRAM内存宽度:16
功能数量:1端口数量:1
端子数量:60字数:8388608 words
字数代码:8000000工作模式:SYNCHRONOUS
最高工作温度:85 °C最低工作温度:-40 °C
组织:8MX16封装主体材料:PLASTIC/EPOXY
封装代码:TFBGA封装形状:RECTANGULAR
封装形式:GRID ARRAY, THIN PROFILE, FINE PITCH座面最大高度:1.2 mm
自我刷新:YES最大供电电压 (Vsup):1.95 V
最小供电电压 (Vsup):1.7 V标称供电电压 (Vsup):1.8 V
表面贴装:YES技术:CMOS
温度等级:INDUSTRIAL端子形式:BALL
端子节距:0.8 mm端子位置:BOTTOM
宽度:8 mmBase Number Matches:1

M53D128168A-7.5BIG2E 数据手册

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ESMT  
M53D128168A (2E)  
Operation Temperature Condition -40°C~85°C  
Mobile DDR SDRAM  
2M x16 Bit x 4 Banks  
Mobile DDR SDRAM  
Features  
z
z
All inputs except data & DM are sampled at the rising  
edge of the system clock(CLK)  
DQS is edge-aligned with data for READ; center-aligned  
with data for WRITE  
Data mask (DM) for write masking only  
VDD/VDDQ = 1.7V ~ 1.95V  
Auto & Self refresh  
z
JEDEC Standard  
z
Internal pipelined double-data-rate architecture, two data  
access per clock cycle  
z
z
Bi-directional data strobe (DQS)  
No DLL; CLK to DQS is not synchronized.  
z
z
z
z
z
z
z
z
z
z
z
Differential clock inputs (CLK and CLK )  
Four bank operation  
CAS Latency : 2, 3  
Burst Type : Sequential and Interleave  
Burst Length : 2, 4, 8, 16  
Special function support  
15.6us refresh interval (64ms refresh period, 4K cycle)  
LVCMOS-compatible inputs  
-
-
PASR (Partial Array Self Refresh)  
Internal TCSR (Temperature Compensated Self  
Refresh)  
-
DS (Drive Strength)  
Ordering Information  
Product ID  
Max Freq.  
200MHz  
166MHz  
133MHz  
VDD  
Package  
Comments  
M53D128168A -5BIG2E  
M53D128168A -6BIG2E  
M53D128168A -7.5BIG2E  
1.8V  
60 ball BGA  
Pb-free  
Functional Block Diagram  
CLK  
Clock  
Generator  
CLK  
Bank D  
Bank C  
Bank B  
CKE  
Row  
Address  
Address  
Buffer  
&
Refresh  
Counter  
Mode Register &  
Extended Mode  
Register  
Bank A  
DQS  
DM  
Sense Amplifier  
Column Decoder  
Column  
Address  
Buffer  
&
Refresh  
Counter  
CS  
RAS  
CAS  
WE  
Data Control Circuit  
DQ  
Elite Semiconductor Memory Technology Inc.  
Publication Date : Jul. 2012  
Revision : 1.0 1/47  

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