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M53D128168A-7.5BAG PDF预览

M53D128168A-7.5BAG

更新时间: 2024-09-25 05:46:55
品牌 Logo 应用领域
晶豪 - ESMT 存储内存集成电路动态存储器双倍数据速率
页数 文件大小 规格书
47页 1094K
描述
2M x 16 Bit x 4 Banks Mobile DDR SDRAM

M53D128168A-7.5BAG 技术参数

生命周期:Contact Manufacturer零件包装代码:BGA
包装说明:TFBGA,针数:60
Reach Compliance Code:unknownECCN代码:EAR99
HTS代码:8542.32.00.02风险等级:5.57
访问模式:FOUR BANK PAGE BURST最长访问时间:7 ns
其他特性:AUTO/SELF REFRESHJESD-30 代码:R-PBGA-B60
长度:13 mm内存密度:134217728 bit
内存集成电路类型:DDR DRAM内存宽度:16
功能数量:1端口数量:1
端子数量:60字数:8388608 words
字数代码:8000000工作模式:SYNCHRONOUS
最高工作温度:70 °C最低工作温度:
组织:8MX16封装主体材料:PLASTIC/EPOXY
封装代码:TFBGA封装形状:RECTANGULAR
封装形式:GRID ARRAY, THIN PROFILE, FINE PITCH认证状态:Not Qualified
座面最大高度:1.2 mm自我刷新:YES
最大供电电压 (Vsup):1.9 V最小供电电压 (Vsup):1.7 V
标称供电电压 (Vsup):1.8 V表面贴装:YES
技术:CMOS温度等级:COMMERCIAL
端子形式:BALL端子节距:0.8 mm
端子位置:BOTTOM宽度:8 mm
Base Number Matches:1

M53D128168A-7.5BAG 数据手册

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ESMT  
Preliminary  
M53D128168A  
Mobile DDR SDRAM  
2M x 16 Bit x 4 Banks  
Mobile DDR SDRAM  
Features  
z
z
JEDEC Standard  
Internal pipelined double-data-rate architecture, two data  
access per clock cycle  
Bi-directional data strobe (DQS)  
No DLL; CLK to DQS is not synchronized.  
z
All inputs except data & DM are sampled at the rising  
edge of the system clock(CLK)  
Data I/O transitions on both edges of data strobe (DQS)  
DQS is edge-aligned with data for READ; center-aligned  
with data for WRITE  
z
z
z
z
z
z
z
z
z
z
Data mask (DM) for write masking only  
VDD/VDDQ = 1.7V ~ 1.9V  
Auto & Self refresh  
15.6us refresh interval (64ms refresh period, 4K cycle)  
1.8V LVCMOS-compatible inputs  
60 ball BGA package  
z
z
z
z
z
z
Differential clock inputs (CLK and CLK )  
Quad bank operation  
CAS Latency : 2, 3  
Burst Type : Sequential and Interleave  
Burst Length : 2, 4, 8  
Special function support  
-
-
PASR (Partial Array Self Refresh)  
Internal TCSR (Temperature Compensated Self  
Refresh)  
-
DS (Driver Strength)  
Ordering information :  
Part NO.  
MAX FREQ  
VDD  
PACKAGE  
8x10 mm  
BGA  
COMMENTS  
Pb-free  
M53D128168A -7.5BG  
M53D128168A -10BG  
M53D128168A -7.5BAG  
M53D128168A -10BAG  
133MHz  
100MHz  
133MHz  
100MHz  
Pb-free  
1.8V  
8x13 mm  
BGA  
Pb-free  
Pb-free  
Functional Block Diagram  
CLK  
Clock  
Generator  
CLK  
Bank D  
Bank C  
Bank B  
CKE  
Row  
Address  
Address  
Buffer  
&
Refresh  
Counter  
Mode Register &  
Extended Mode  
Register  
Bank A  
DQS  
DM  
Sense Amplifier  
Column Decoder  
Column  
Address  
Buffer  
&
Refresh  
Counter  
CS  
RAS  
CAS  
WE  
Data Control Circuit  
DQ  
Elite Semiconductor Memory Technology Inc.  
Publication Date : Sep. 2008  
Revision : 1.4 1/47  

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