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M53D128168A-5BG2E PDF预览

M53D128168A-5BG2E

更新时间: 2024-11-13 20:53:23
品牌 Logo 应用领域
晶豪 - ESMT 时钟动态存储器双倍数据速率内存集成电路
页数 文件大小 规格书
47页 1137K
描述
DDR DRAM, 8MX16, 5ns, CMOS, PBGA60, 8 X 13 MM, 1.20 MM HEIGHT, 0.80 MM PITCH, LEAD FREE, BGA-60

M53D128168A-5BG2E 技术参数

生命周期:Contact Manufacturer包装说明:BGA-60
Reach Compliance Code:unknown风险等级:5.69
访问模式:FOUR BANK PAGE BURST最长访问时间:5 ns
其他特性:AUTO/SELF REFRESH最大时钟频率 (fCLK):200 MHz
I/O 类型:COMMON交错的突发长度:2,4,8,16
JESD-30 代码:R-PBGA-B60长度:13 mm
内存密度:134217728 bit内存集成电路类型:DDR DRAM
内存宽度:16功能数量:1
端口数量:1端子数量:60
字数:8388608 words字数代码:8000000
工作模式:SYNCHRONOUS最高工作温度:70 °C
最低工作温度:组织:8MX16
输出特性:3-STATE封装主体材料:PLASTIC/EPOXY
封装代码:VBGA封装等效代码:BGA60,6X12,40/32
封装形状:RECTANGULAR封装形式:GRID ARRAY, VERY THIN PROFILE
刷新周期:4096反向引出线:NO
座面最大高度:1 mm自我刷新:YES
连续突发长度:2,4,8,16最小待机电流:1.7 V
最大供电电压 (Vsup):1.95 V最小供电电压 (Vsup):1.7 V
标称供电电压 (Vsup):1.8 V表面贴装:YES
技术:CMOS温度等级:COMMERCIAL
端子形式:BALL端子节距:1 mm
端子位置:BOTTOM宽度:8 mm
Base Number Matches:1

M53D128168A-5BG2E 数据手册

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ESMT  
M53D128168A (2E)  
Mobile DDR SDRAM  
2M x16 Bit x 4 Banks  
Mobile DDR SDRAM  
Features  
z
z
All inputs except data & DM are sampled at the rising  
edge of the system clock(CLK)  
DQS is edge-aligned with data for READ; center-aligned  
with data for WRITE  
Data mask (DM) for write masking only  
VDD/VDDQ = 1.7V ~ 1.95V  
Auto & Self refresh  
z
JEDEC Standard  
z
Internal pipelined double-data-rate architecture, two data  
access per clock cycle  
z
z
Bi-directional data strobe (DQS)  
No DLL; CLK to DQS is not synchronized.  
z
z
z
z
z
z
z
z
z
z
z
Differential clock inputs (CLK and CLK )  
Four bank operation  
CAS Latency : 2, 3  
Burst Type : Sequential and Interleave  
Burst Length : 2, 4, 8, 16  
Special function support  
15.6us refresh interval (64ms refresh period, 4K cycle)  
LVCMOS-compatible inputs  
-
-
PASR (Partial Array Self Refresh)  
Internal TCSR (Temperature Compensated Self  
Refresh)  
-
DS (Drive Strength)  
Ordering Information  
Product ID  
Max Freq.  
200MHz  
166MHz  
133MHz  
VDD  
Package  
Comments  
M53D128168A -5BG2E  
M53D128168A -6BG2E  
M53D128168A -7.5BG2E  
1.8V  
60 ball BGA  
Pb-free  
Functional Block Diagram  
CLK  
Clock  
Generator  
CLK  
Bank D  
Bank C  
Bank B  
CKE  
Row  
Address  
Address  
Buffer  
&
Refresh  
Counter  
Mode Register &  
Extended Mode  
Register  
Bank A  
DQS  
DM  
Sense Amplifier  
Column Decoder  
Column  
Address  
Buffer  
&
Refresh  
Counter  
CS  
RAS  
CAS  
WE  
Data Control Circuit  
DQ  
Elite Semiconductor Memory Technology Inc.  
Publication Date : Jul. 2012  
Revision : 1.0 1/47  

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