Datasheet > M52S64322A

M52S64322A

更新时间： 2024-02-24 23:01:32

品牌	Logo	应用领域
晶豪 - ESMT		动态存储器手机
页数	文件大小	规格书
47页	1234K
描述
512K x 32 Bit x 4 Banks Mobile Synchronous DRAM

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M52S64322A 数据手册

ESMT

M52S64322A

512K x 32 Bit x 4 Banks

Mobile Synchronous DRAM

Mobile SDRAM

FEATURES

ORDERING INFORMATION

MAX

2.5V power supply

LVTTL compatible with multiplexed address

Four banks operation

MRS cycle with address key programs

- CAS Latency (2 & 3)

PRODUCT NO.

PACKAGE Comments

FREQ.

M52S64322A-7.5BG 133MHz 90 Ball FBGA

M52S64322A-10BG 100MHz 90 Ball FBGA

Pb-free

- Burst Length (1, 2, 4, 8 & full page)

- Burst Type (Sequential & Interleave)

EMRS cycle with address

All inputs are sampled at the positive going edge of the

system clock

Special function support

PASR (Partial Array Self Refresh)

TCSR (Temperature Compensated Self Refresh)

DS (Driver Strength)

DQM for masking

Auto & self refresh

64ms refresh period (4K cycle)

GENERAL DESCRIPTION

The M52S64322A is 67,108,864 bits synchronous high data rate Dynamic RAM organized as 4 x 524,288 words by

32 bits. Synchronous design allows precise cycle controls with the use of system clock I/O transactions are possible on

every clock cycle. Range of operating frequencies, programmable burst length and programmable latencies allow the

same device to be useful for a variety of high bandwidth, high performance memory system applications.

PIN ASSIGNMENT

90 Ball FBGA

DQ26 DQ24 VSS

DQ28 VDDQ VSSQ

VSSQ DQ27 DQ25

VSSQ DQ29 DQ30

VDDQ DQ31 NC

VSS DQM3 A3

VDD DQ23 DQ21

VDDQ VSSQ DQ19

DQ22 DQ20 VDDQ

DQ17 DQ18 VDDQ

NC DQ16 VSSQ

A2 DQM2 VDD

A10

BA1

CLK CKE

DQM1 NC

BA0

CAS

RAS

DQM0

VDDQ DQ8 VSS

VSSQ DQ10 DQ9

VSSQ DQ12 DQ14

DQ11 VDDQ VSSQ

DQ13 DQ15 VSS

VDD DQ7 VSSQ

DQ6 DQ5 VDDQ

DQ1 DQ3 VDDQ

VDDQ VSSQ DQ4

VDD DQ0 DQ2

Elite Semiconductor Memory Technology Inc.

Publication Date: Aug. 2009

Revision: 1.3 1/47

12 3 4 5 6 7...47

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