ESMT
M52S32321A
SDRAM
512K x 32Bit x 2Banks
Synchronous DRAM
FEATURES
GENERAL DESCRIPTION
The M52S32321A is 33,554,432 bits synchronous high data
rate Dynamic RAM organized as 2 x 524,288 words by 32 bits,
fabricated with high performance CMOS technology.
Synchronous design allows precise cycle control with the use of
system clock I/O transactions are possible on every clock cycle.
Range of operating frequencies, programmable burst length and
programmable latencies allow the same device to be useful for
a variety of high bandwidth, high performance memory system
applications.
z
z
z
z
2.5V power supply
LVCMOS compatible with multiplexed address
Dual banks operation
MRS cycle with address key programs
-
-
-
CAS Latency (1, 2 & 3 )
Burst Length (1, 2, 4, 8 & full page)
Burst Type (Sequential & Interleave)
z
z
EMRS cycle with address key programs.
All inputs are sampled at the positive going edge of the
system clock
z
z
Burst Read Single-bit Write operation
Special Function Support.
ORDERING INFORMATION
-
-
-
PASR (Partial Array Self Refresh )
TCSR (Temperature compensated Self Refresh)
DS (Driver Strength)
Max
Freq.
Product ID
Package
Comments
M52S32321A -10BG
100MHz 90 Ball BGA
Pb-free
Pb-free
Pb-free
z
z
z
DQM for masking
Auto & self refresh
64ms refresh period (4K cycle)
M52S32321A -7.5BG 133MHz 90 Ball BGA
M52S32321A -6BG 166MHz 90 Ball BGA
PIN CONFIGURATION (TOP VIEW)
90 Ball BGA
1
2
3
4
5
6
7
8
9
A
B
C
D
E
F
DQ26 DQ24 VSS
DQ28 VDDQ VSSQ
VSSQ DQ27 DQ25
VSSQ DQ29 DQ30
VDDQ DQ31 NC
VSS DQM3 A3
VDD DQ23 DQ21
VDDQ VSSQ DQ19
DQ22 DQ20 VDDQ
DQ17 DQ18 VDDQ
NC DQ16 VSSQ
A2 DQM2 VDD
G
H
J
A4
A7
A5
A8
A6
NC
A9
A10
NC
A0
NC
CS
WE
A1
NC
CLK CKE
DQM1 NC
BA
RAS
DQM0
K
L
NC
CAS
VDDQ DQ8 VSS
VSSQ DQ10 DQ9
VSSQ DQ12 DQ14
DQ11 VDDQ VSSQ
DQ13 DQ15 VSS
VDD DQ7 VSSQ
DQ6 DQ5 VDDQ
DQ1 DQ3 VDDQ
VDDQ VSSQ DQ4
VDD DQ0 DQ2
M
N
P
R
Elite Semiconductor Memory Technology Inc.
Publication Date : Jan. 2009
Revision : 1.5 1/29