Datasheet > M52S128324A

M52S128324A

更新时间： 2024-11-29 05:46:55

品牌	Logo	应用领域
晶豪 - ESMT		动态存储器
页数	文件大小	规格书
47页	750K
描述
1M x 32 Bit x 4 Banks Synchronous DRAM

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数据手册

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M52S128324A 数据手册

ESMT

SDRAM

M52S128324A

1M x 32 Bit x 4 Banks

Synchronous DRAM

FEATURES

ORDERING INFORMATION

JEDEC standard 2.5V power supply

LVTTL compatible with multiplexed address

Four banks operation

MRS cycle with address key programs

- CAS Latency (1, 2 & 3 )

- Burst Length ( 1, 2, 4, 8 & full page )

- Burst Type ( Sequential & Interleave )

All inputs are sampled at the positive going edge of the

system clock

MAX

FREQ.

Product No.

PACKAGE COMMENTS

M52S128324A-7TG 143MHz 86 TSOPII

M52S128324A-7BG 143MHz 90 FBGA

M52S128324A-10TG 100MHz 86 TSOPII

M52S128324A-10BG 100MHz 90 FBGA

Pb-free

Special function support

- PASR (Partial Array Self Refresh)

- TCSR (Temperature compensated Self Refresh)

Issued by EMRS

- DS (Driver Strength)

DQM for masking

Auto & self refresh

64ms refresh period (4K cycle)

GENERAL DESCRIPTION

The M52S128324A is 134,217,728 bits synchronous high data rate Dynamic RAM organized as 4 x 1,048,576 words by 32 bits.

Synchronous design allows precise cycle control with the use of system clock I/O transactions are possible on every clock cycle.

Range of operating frequencies, programmable burst length and programmable latencies allow the same device to be useful for a

variety of high bandwidth, high performance memory system applications.

Elite Semiconductor Memory Technology Inc.

Publication Date: Mar. 2009

Revision: 1.4 1/47

12 3 4 5 6 7...47

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与M52S128324A相关器件

型号	品牌	获取价格	描述	数据表
M52S128324A-10BG	ESMT	获取价格	1M x 32 Bit x 4 Banks Synchronous DRAM
M52S128324A-10TG	ESMT	获取价格	1M x 32 Bit x 4 Banks Synchronous DRAM
M52S128324A-7BG	ESMT	获取价格	1M x 32 Bit x 4 Banks Synchronous DRAM
M52S128324A-7TG	ESMT	获取价格	1M x 32 Bit x 4 Banks Synchronous DRAM
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M52S16161A-10BG	ESMT	获取价格	512K x 16Bit x 2Banks Synchronous DRAM
M52S16161A-10TG	ESMT	获取价格	512K x 16Bit x 2Banks Synchronous DRAM
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