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M52D64322A-10BG PDF预览

M52D64322A-10BG

更新时间: 2024-09-24 05:46:55
品牌 Logo 应用领域
晶豪 - ESMT 存储内存集成电路动态存储器手机
页数 文件大小 规格书
46页 1182K
描述
512K x 32 Bit x 4 Banks Mobile Synchronous DRAM

M52D64322A-10BG 技术参数

生命周期:Contact Manufacturer零件包装代码:BGA
包装说明:VFBGA,针数:90
Reach Compliance Code:unknownECCN代码:EAR99
HTS代码:8542.32.00.02风险等级:5.73
Is Samacsys:N访问模式:FOUR BANK PAGE BURST
最长访问时间:9 ns其他特性:AUTO/SELF REFRESH
JESD-30 代码:R-PBGA-B90长度:13 mm
内存密度:67108864 bit内存集成电路类型:SYNCHRONOUS DRAM
内存宽度:32功能数量:1
端口数量:1端子数量:90
字数:2097152 words字数代码:2000000
工作模式:SYNCHRONOUS最高工作温度:70 °C
最低工作温度:组织:2MX32
封装主体材料:PLASTIC/EPOXY封装代码:VFBGA
封装形状:RECTANGULAR封装形式:GRID ARRAY, VERY THIN PROFILE, FINE PITCH
认证状态:Not Qualified座面最大高度:1 mm
自我刷新:YES最大供电电压 (Vsup):1.9 V
最小供电电压 (Vsup):1.7 V标称供电电压 (Vsup):1.8 V
表面贴装:YES技术:CMOS
温度等级:COMMERCIAL端子形式:BALL
端子节距:0.8 mm端子位置:BOTTOM
宽度:8 mmBase Number Matches:1

M52D64322A-10BG 数据手册

 浏览型号M52D64322A-10BG的Datasheet PDF文件第2页浏览型号M52D64322A-10BG的Datasheet PDF文件第3页浏览型号M52D64322A-10BG的Datasheet PDF文件第4页浏览型号M52D64322A-10BG的Datasheet PDF文件第5页浏览型号M52D64322A-10BG的Datasheet PDF文件第6页浏览型号M52D64322A-10BG的Datasheet PDF文件第7页 
ESMT  
Mobile SDRAM  
M52D64322A  
512K x 32 Bit x 4 Banks  
Mobile Synchronous DRAM  
ORDERING INFORMATION  
FEATURES  
y
y
y
y
1.8V power supply  
LVTTL compatible with multiplexed address  
Four banks operation  
MRS cycle with address key programs  
- CAS Latency (2 & 3)  
Product ID  
Max Freq.  
Package  
Comments  
M52D64322A-10BG  
100MHz 90 Ball FBGA  
Pb-free  
- Burst Length (1, 2, 4, 8 & full page)  
- Burst Type (Sequential & Interleave)  
EMRS cycle with address  
All inputs are sampled at the positive going edge of the  
system clock  
y
y
y
Special function support  
-
-
-
PASR (Partial Array Self Refresh)  
TCSR (Temperature Compensated Self Refresh)  
DS (Driver Strength)  
y
y
y
DQM for masking  
Auto & self refresh  
64ms refresh period (4K cycle)  
GENERAL DESCRIPTION  
The M52D64322A is 67,108,864 bits synchronous high data rate Dynamic RAM organized as 4 x 524,288 words by  
32 bits. Synchronous design allows precise cycle controls with the use of system clock I/O transactions are possible on  
every clock cycle. Range of operating frequencies, programmable burst length and programmable latencies allow the same  
device to be useful for a variety of high bandwidth, high performance memory system applications.  
PIN ASSIGNMENT  
90 Ball FBGA  
1
2
3
4
5
6
7
8
9
A
B
C
D
E
F
DQ26 DQ24 VSS  
DQ28 VDDQ VSSQ  
VSSQ DQ27 DQ25  
VSSQ DQ29 DQ30  
VDDQ DQ31 NC  
VSS DQM3 A3  
VDD DQ23 DQ21  
VDDQ VSSQ DQ19  
DQ22 DQ20 VDDQ  
DQ17 DQ18 VDDQ  
NC DQ16 VSSQ  
A2 DQM2 VDD  
G
H
J
A4  
A7  
A5  
A8  
A6  
NC  
A9  
A10  
NC  
A0  
BA1  
CS  
A1  
NC  
CLK CKE  
DQM1 NC  
BA0  
CAS  
RAS  
DQM0  
K
L
NC  
WE  
VDDQ DQ8 VSS  
VSSQ DQ10 DQ9  
VSSQ DQ12 DQ14  
DQ11 VDDQ VSSQ  
DQ13 DQ15 VSS  
VDD DQ7 VSSQ  
DQ6 DQ5 VDDQ  
DQ1 DQ3 VDDQ  
VDDQ VSSQ DQ4  
VDD DQ0 DQ2  
M
N
P
R
Elite Semiconductor Memory Technology Inc.  
Publication Date: Jan. 2009  
Revision: 1.4 1/46  

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