Datasheet > M52D5121632A-5BG

M52D5121632A-5BG

更新时间： 2024-02-05 20:59:45

品牌	Logo	应用领域
晶豪 - ESMT		动态存储器
页数	文件大小	规格书
46页	1185K
描述
8M x 16 Bit x 4 Banks Mobile Synchronous DRAM

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中文翻译

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数据手册

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M52D5121632A-5BG 数据手册

ESMT

M52D5121632A

8M x 16 Bit x 4 Banks

Mobile Synchronous DRAM

Mobile SDRAM

ORDERING INFORMATION

FEATURES

1.8V power supply

LVCMOS compatible with multiplexed address

Four banks operation

Product ID

Max Freq.

Package

Comments

Pb-free

M52D5121632A-5BG

M52D5121632A-6BG

M52D5121632A-7BG

200MHz 54 Ball FBGA

166MHz 54 Ball FBGA

143MHz 54 Ball FBGA

MRS cycle with address key programs

Pb-free

CAS Latency (2, 3)

Pb-free

Burst Length (1, 2, 4, 8 & full page)

Burst Type (Sequential & Interleave)

EMRS cycle with address

All inputs are sampled at the positive going edge of the

system clock

Special function support

PASR (Partial Array Self Refresh)

TCSR (Temperature Compensated Self Refresh)

DS (Driver Strength)

Deep Power Down (DPD) Mode

DQM for masking

Auto & self refresh

64ms refresh period (8K cycle)

GENERAL DESCRIPTION

The M52D5121632A is 536,870,912 bits synchronous high data rate Dynamic RAM organized as 4 x 8,388,608 words by

16 bits. Synchronous design allows precise cycle controls with the use of system clock I/O transactions are possible on

every clock cycle. Range of operating frequencies, programmable burst lengths and programmable latencies allow the

same device to be useful for a variety of high bandwidth, high performance memory system applications.

BALL CONFIGURATION (TOP VIEW)

(BGA54, 8mmX8mmX1mm Body, 0.8mm Ball Pitch)

VDDQ

DQ15

VSSQ

DQ0

VDD

VSS

VSSQ

VDDQ

DQ2

DQ4

DQ1

DQ3

DQ14

DQ12

DQ13

DQ11

VDDQ

VSSQ

VDD

VDDQ

VSS

DQ6

DQ10

DQ8

DQ9

DQ5

DQ7

LDQM

UDQM

A12

CLK

A11

CKE

CAS

BA0

RAS

BA1

A10

VSS

VDD

Elite Semiconductor Memory Technology Inc.

Publication Date: Jan. 2016

Revision: 1.1 1/46

12 3 4 5 6 7...46

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与M52D5121632A-5BG相关器件

型号	品牌	获取价格	描述	数据表
M52D5121632A-6BG	ESMT	获取价格	8M x 16 Bit x 4 Banks Mobile Synchronous DRAM
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