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M52D16161A

更新时间: 2024-01-28 09:28:00
品牌 Logo 应用领域
晶豪 - ESMT 动态存储器
页数 文件大小 规格书
29页 757K
描述
512K x 16Bit x 2Banks Synchronous DRAM

M52D16161A 数据手册

 浏览型号M52D16161A的Datasheet PDF文件第2页浏览型号M52D16161A的Datasheet PDF文件第3页浏览型号M52D16161A的Datasheet PDF文件第4页浏览型号M52D16161A的Datasheet PDF文件第5页浏览型号M52D16161A的Datasheet PDF文件第6页浏览型号M52D16161A的Datasheet PDF文件第7页 
ESMT  
M52D16161A  
SDRAM  
512K x 16Bit x 2Banks  
Synchronous DRAM  
FEATURES  
GENERAL DESCRIPTION  
The M52D16161A is 16,777,216 bits synchronous high  
data rate Dynamic RAM organized as 2 x 524,288 words by  
16 bits, fabricated with high performance CMOS technology.  
Synchronous design allows precise cycle control with the  
use of system clock I/O transactions are possible on every  
clock cycle. Range of operating frequencies, programmable  
burst length and programmable latencies allow the same  
device to be useful for a variety of high bandwidth, high  
performance memory system applications.  
z
z
z
z
1.8V power supply  
LVCMOS compatible with multiplexed address  
Dual banks operation  
MRS cycle with address key programs  
-
-
-
CAS Latency (1, 2 & 3 )  
Burst Length (1, 2, 4, 8 & full page)  
Burst Type (Sequential & Interleave)  
z
z
EMRS cycle with address key programs.  
All inputs are sampled at the positive going edge of the  
system clock  
z
z
Burst Read Single-bit Write operation  
Special Function Support.  
ORDERING INFORMATION  
-
-
-
PASR (Partial Array Self Refresh )  
TCSR (Temperature compensated Self Refresh)  
DS (Driver Strength)  
MAX  
Freq.  
Part NO.  
Package  
Comments  
M52D16161A-10TG 100MHz 50 PIN TSOP(II)  
M52D16161A-10BG 100MHz 60 Ball VFBGA  
Pb-free  
Pb-free  
z
z
z
DQM for masking  
Auto & self refresh  
32ms refresh period (2K cycle)  
PIN CONFIGURATION (TOP VIEW)  
1
2
3
4
5
6
7
DQ0  
DQ15  
VDD  
A
B
VSS  
VDD  
1
VSS  
50  
49  
48  
47  
46  
45  
44  
43  
42  
41  
40  
39  
38  
37  
36  
35  
34  
33  
32  
31  
30  
29  
28  
27  
26  
DQ0  
DQ1  
VSSQ  
DQ2  
DQ3  
VDDQ  
DQ4  
DQ5  
VSSQ  
DQ6  
DQ7  
VDDQ  
LDQM  
WE  
2
DQ15  
DQ14  
VSSQ  
DQ13  
DQ12  
VDDQ  
DQ11  
DQ10  
VSSQ  
DQ9  
DQ8  
VDDQ  
N.C/RFU  
UDQM  
CLK  
CKE  
N.C  
VDDQ  
VSSQ  
DQ1  
DQ2  
DQ14  
DQ13  
VSSQ  
VDDQ  
3
4
C
D
E
F
5
6
7
DQ4  
DQ3  
DQ5  
DQ12  
DQ10  
DQ9  
DQ11  
8
9
VDDQ  
VSSQ  
10  
11  
12  
13  
14  
15  
16  
17  
18  
19  
20  
21  
22  
23  
24  
25  
VSSQ  
NC  
VDDQ  
NC  
DQ6  
DQ7  
G
H
J
DQ8  
NC  
NC  
NC  
NC  
NC  
WE  
CAS  
RAS  
CS  
UDQM  
LDQM  
BA  
A9  
NC  
CLK  
NC  
A9  
RAS  
NC  
CAS  
CS  
K
L
A10/AP  
A0  
A8  
A7  
CKE  
A1  
A6  
A2  
A5  
A3  
A4  
50PIN TSOP(II)  
(400mil x 825mil)  
(0.8 mm PIN PITCH)  
NC  
A0  
NC  
A11  
A8  
M
N
P
R
VDD  
VSS  
A10  
A7  
A1  
A6  
A5  
A4  
A2  
A3  
60 Ball VFBGA  
(6.4x10.1mm)  
(0.65mm ball pitch)  
VSS  
VDD  
Elite Semiconductor Memory Technology Inc.  
Publication Date : Apr. 2007  
Revision : 1.5 1/29  

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