ESMT
M52D128168A
Mobile SDRAM
2M x 16 Bit x 4 Banks
Mobile Synchronous DRAM
FEATURES
ORDERING INFORMATION
y
y
y
y
1.8V power supply
LVCMOS compatible with multiplexed address
Four banks operation
MRS cycle with address key programs
- CAS Latency (2 & 3)
Product ID
Max Freq.
Package
Comments
Pb-free
Pb-free
Pb-free
Pb-free
Pb-free
Pb-free
M52D128168A-7TG
M52D128168A-7BG
143MHz
54 TSOP II
- Burst Length (1, 2, 4, 8 & full page)
- Burst Type (Sequential & Interleave)
EMRS cycle with address
All inputs are sampled at the positive going edge of the
system clock
143MHz 54 Ball FBGA
54 TSOP II
M52D128168A-7.5BG 133MHz 54 Ball FBGA
M52D128168A-10TG 100MHz 54 TSOP II
M52D128168A-10BG 100MHz 54 Ball FBGA
y
y
M52D128168A-7.5TG 133MHz
y
Special function support
-
-
-
PASR (Partial Array Self Refresh)
TCSR (Temperature Compensated Self Refresh)
DS (Driver Strength)
y
y
y
DQM for masking
Auto & self refresh
64ms refresh period (4K cycle)
GENERAL DESCRIPTION
The M52D128168A is 134,217,728 bits synchronous high data rate Dynamic RAM organized as 4 x 2,097,152
words by 16 bits. Synchronous design allows precise cycle controls with the use of system clock I/O transactions are
possible on every clock cycle. Range of operating frequencies, programmable burst lengths and programmable latencies
allow the same device to be useful for a variety of high bandwidth, high performance memory system applications.
PIN ASSIGNMENT (Top View)
1
2
3
4
5
6
7
8
9
VDD
DQ0
VDDQ
DQ1
DQ2
VSSQ
DQ3
DQ4
VDDQ
1
2
3
4
5
6
7
8
9
54
53 DQ15
52 VSSQ
VSS
VSSQ
VDDQ
DQ0
VDD
A
B
C
D
E
F
VSS
DQ15
51 DQ14
50 DQ13
VDDQ
VSSQ
VSSQ
VDDQ
DQ2
DQ4
DQ1
DQ3
DQ14
DQ12
DQ13
DQ11
49
48
VDDQ
DQ12
47 DQ11
46 VSSQ
VSSQ
VDD
DQ6
DQ10
DQ8
DQ9
NC
VDDQ
VSS
CKE
A9
DQ5
DQ7
45 DQ10
44 DQ9
DQ5 10
DQ6 11
LDQM
43
42 DQ8
41 VSS
VDDQ
VSSQ
DQ7 13
VDD 14
12
UDQM
NC
CLK
A11
CAS
BA0
RAS
BA1
WE
CS
LDQM 15
WE 16
40 NC
G
H
J
39 UDQM
38 CLK
37 CKE
36 NC
CAS 17
RAS 18
CS 19
A8
A0
A3
A10
A7
A5
A6
A4
A1
A2
35
34
33
32
31
30
29
28
A11
A9
BA0 20
BA1 21
A10/AP 22
54 Ball FBGA
(8x8mm)
(mm ball pitch)
VSS
VDD
A8
A0
A1
23
24
25
26
27
A7
A6
A2
A5
A4
A3
VDD
VSS
Elite Semiconductor Memory Technology Inc.
Publication Date: Aug. 2009
Revision: 1.3 1/48