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M52D128168A-7BG2E PDF预览

M52D128168A-7BG2E

更新时间: 2024-01-08 10:07:19
品牌 Logo 应用领域
晶豪 - ESMT 动态存储器内存集成电路
页数 文件大小 规格书
47页 1168K
描述
Synchronous DRAM, 8MX16, 6ns, CMOS, PBGA54, 8 X 8 MM, 1 MM HEIGHT, 0.80 MM PITCH, LEAD FREE, FBGA-54

M52D128168A-7BG2E 技术参数

生命周期:Contact Manufacturer包装说明:VFBGA,
Reach Compliance Code:unknown风险等级:5.7
访问模式:FOUR BANK PAGE BURST最长访问时间:6 ns
其他特性:AUTO/SELF REFRESHJESD-30 代码:S-PBGA-B54
长度:8 mm内存密度:134217728 bit
内存集成电路类型:SYNCHRONOUS DRAM内存宽度:16
功能数量:1端口数量:1
端子数量:54字数:8388608 words
字数代码:8000000工作模式:SYNCHRONOUS
最高工作温度:70 °C最低工作温度:
组织:8MX16封装主体材料:PLASTIC/EPOXY
封装代码:VFBGA封装形状:SQUARE
封装形式:GRID ARRAY, VERY THIN PROFILE, FINE PITCH座面最大高度:1 mm
自我刷新:YES最大供电电压 (Vsup):1.95 V
最小供电电压 (Vsup):1.7 V标称供电电压 (Vsup):1.8 V
表面贴装:YES技术:CMOS
温度等级:COMMERCIAL端子形式:BALL
端子节距:0.8 mm端子位置:BOTTOM
宽度:8 mmBase Number Matches:1

M52D128168A-7BG2E 数据手册

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ESMT  
M52D128168A (2E)  
2M x 16 Bit x 4 Banks  
Mobile Synchronous DRAM  
Mobile SDRAM  
ORDERING INFORMATION  
FEATURES  
y
y
y
y
1.8V power supply  
LVCMOS compatible with multiplexed address  
Four banks operation  
MRS cycle with address key programs  
- CAS Latency (2 & 3)  
- Burst Length (1, 2, 4, 8 & full page)  
- Burst Type (Sequential & Interleave)  
EMRS cycle with address  
Product ID  
Max Freq.  
Package  
Comments  
Pb-free  
M52D128168A-5BG2E 200MHz 54 Ball FBGA  
M52D128168A-6BG2E 166MHz 54 Ball FBGA  
M52D128168A-7BG2E 143MHz 54 Ball FBGA  
Pb-free  
Pb-free  
y
y
All inputs are sampled at the positive going edge of the  
system clock  
y
Special function support  
-
-
-
PASR (Partial Array Self Refresh)  
TCSR (Temperature Compensated Self Refresh)  
DS (Driver Strength)  
y
y
y
DQM for masking  
Auto & self refresh  
64ms refresh period (4K cycle)  
GENERAL DESCRIPTION  
The M52D128168A is 134,217,728 bits synchronous high data rate Dynamic RAM organized as 4 x 2,097,152  
words by 16 bits. Synchronous design allows precise cycle controls with the use of system clock I/O transactions are  
possible on every clock cycle. Range of operating frequencies, programmable burst lengths and programmable latencies  
allow the same device to be useful for a variety of high bandwidth, high performance memory system applications.  
BALL CONFIGURATION (TOP VIEW)  
(BGA54, 8mmX8mmX1mm Body, 0.8mm Ball Pitch)  
1
2
3
4
5
6
7
8
9
VDDQ  
DQ15  
VSSQ  
DQ0  
VDD  
A
B
VSS  
VSSQ  
VDDQ  
DQ2  
DQ4  
DQ1  
DQ3  
DQ14  
DQ12  
DQ13  
DQ11  
VDDQ  
VSSQ  
C
D
E
F
VSSQ  
VDD  
VDDQ  
VSS  
DQ6  
DQ10  
DQ8  
DQ9  
NC  
DQ5  
DQ7  
LDQM  
UDQM  
NC  
CLK  
A11  
CKE  
A9  
CAS  
BA0  
RAS  
BA1  
WE  
CS  
G
H
J
A8  
A10  
A7  
A5  
A6  
A4  
A0  
A3  
A1  
A2  
VSS  
VDD  
Elite Semiconductor Memory Technology Inc.  
Publication Date: Aug. 2012  
Revision: 1.0 1/47  

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