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M52338FP PDF预览

M52338FP

更新时间: 2024-02-28 12:39:32
品牌 Logo 应用领域
三菱 - MITSUBISHI 消费电路商用集成电路光电二极管
页数 文件大小 规格书
12页 138K
描述
INTERFACE IC FOR ACTIVE MATRIX LIQUID CRYSTAL PANEL

M52338FP 技术参数

是否Rohs认证: 不符合生命周期:Obsolete
零件包装代码:SOIC包装说明:SSOP,
针数:32Reach Compliance Code:unknown
HTS代码:8542.39.00.01风险等级:5.92
Is Samacsys:N商用集成电路类型:CONSUMER CIRCUIT
JESD-30 代码:R-PDSO-G32JESD-609代码:e0
长度:12.8 mm功能数量:1
端子数量:32最高工作温度:70 °C
最低工作温度:-20 °C封装主体材料:PLASTIC/EPOXY
封装代码:SSOP封装形状:RECTANGULAR
封装形式:SMALL OUTLINE, SHRINK PITCH认证状态:Not Qualified
座面最大高度:2.55 mm最大压摆率:75 mA
最大供电电压 (Vsup):5.5 V最小供电电压 (Vsup):4 V
表面贴装:YES温度等级:COMMERCIAL
端子面层:Tin/Lead (Sn/Pb)端子形式:GULL WING
端子节距:0.8 mm端子位置:DUAL
宽度:7.5 mmBase Number Matches:1

M52338FP 数据手册

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MITSUBISHI ICs (TV)  
M52338FP  
INTERFACE IC FOR ACTIVE MATRIX LIQUID CRYSTAL PANEL  
DESCRIPTION  
PIN CONFIGURATION (TOP VIEW)  
The M52338FP is a semiconductor integrated circuit containing an  
interface circuit which is necessary to drive an active matrix liquid  
crystal panel.  
1
2
32  
31  
30  
29  
28  
27  
26  
25  
24  
23  
22  
21  
20  
19  
18  
17  
MAIN IN R  
CLAMP R  
VCC1  
EXT IN R  
FEATURES  
3
MAIN IN G  
CLAMP G  
SUB CONTRAST B  
EXT IN G  
γ correction circuit is built in to correct non-linearity of luminance  
characteristics caused by applied voltage which is peculiar to a  
liquid crystal panel.  
4
5
MAIN IN B  
CLAMP B  
SUB CONTRAST R  
EXT IN R  
6
2
By combining with Mitsubishi video/chroma signal processing  
ICs, M52042FP (NTSC) and M52045FP (PAL), low cost and  
optimal system configuration is possible.  
7
MAIN/EXT SW  
HD IN  
γ
1
8
γ
9
CP CONT.  
VCC2  
CONTRAST  
BRIGHT  
10  
11  
12  
13  
14  
15  
16  
VEE  
FRP1 IN  
R OUT  
APPLICATION  
Active matrix liquid crystal color television  
FRP2 IN  
COMMON GAIN CONT.  
COMMON OUT  
BIAS CONT.  
GND  
SUB BIAS R  
G OUT  
RECOMMENDED OPERATING CONDITION  
SUB BIAS B  
B OUT  
Operating  
supply voltage supply voltage  
Recommended  
Supply voltage  
VCC1  
VCC2  
VEE  
4.0 to 5.5V  
-7.0 to 8.5V  
4.5V  
Outline 32P2U-B  
GND=0V,VCC1=VCC2  
-7.5V  
BLOCK DIAGRAM  
SUB  
BIAS  
R
SUB  
BIAS  
B
SUB  
SUB  
CONTRAST CONTRAST  
CLAMP G  
SW  
7
1
2
R
B
γ
γ
BRIGHT CLAMP R  
CLAMP B  
6
25  
26  
28  
30 23  
2
4
20  
18  
DRIVE BUFFER  
PEAK LIMITER  
BRIGHT  
CLAMP  
R OUT  
G OUT  
MAIN IN R  
MAIN IN G  
MAIN IN B  
EXT IN R  
EXT IN G  
EXT IN B  
1
3
21  
19  
γ-AMP  
CONTRAST  
CONTRAST  
CONTRAST  
SUB BIAS  
SUB BIAS  
CP  
CP  
CP  
CP  
CP  
CP  
MAIN  
EXT  
5
DRIVE BUFFER  
PEAK LIMITER  
BRIGHT  
CLAMP  
γ-AMP  
27  
29  
31  
SW  
DRIVE BUFFER  
PEAK LIMITER  
BRIGHT  
CLAMP  
B OUT  
17  
15  
γ-AMP  
SUB BIAS  
FRP1  
C P  
HO IN  
8
C P  
BIAS  
CONT.  
COMMON  
INV  
FRP2 IN  
12  
CLAMP  
11  
13 14  
9
24  
32  
16  
22  
10  
COMMON GAIN COMMON  
CONT. OUT  
CP  
CONT.  
CONTRAST VCC1  
GND  
FRP1 IN  
VCC2  
VEE  

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