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M50LPW116N5T PDF预览

M50LPW116N5T

更新时间: 2024-11-03 22:26:11
品牌 Logo 应用领域
意法半导体 - STMICROELECTRONICS 闪存
页数 文件大小 规格书
36页 260K
描述
16 Mbit 2Mb x8, Boot Block 3V Supply Low Pin Count Flash Memory

M50LPW116N5T 数据手册

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M50LPW116  
16 Mbit (2Mb x8, Boot Block)  
3V Supply Low Pin Count Flash Memory  
PRELIMINARY DATA  
SUPPLY VOLTAGE  
– V = 3V to 3.6V for Program, Erase and  
CC  
Read Operations  
– V = 12V for Fast Program and Fast Erase  
PP  
TWO INTERFACES  
– Low Pin Count (LPC) Standard Interface for  
embedded operation with PC Chipsets.  
– Address/Address Multiplexed (A/A Mux) In-  
terface for programming equipment compati-  
bility.  
TSOP40 (N)  
10 x 20mm  
LOW PIN COUNT (LPC) HARDWARE  
INTERFACE MODE  
– 5 Signal Communication Interface supporting  
Read and Write Operations  
– Hardware Write Protect Pins for Block Pro-  
tection  
Figure 1. Logic Diagram (LPC Interface)  
– Register Based Read and Write Protection  
– 5 Additional General Purpose Inputs for plat-  
form design flexibility  
V
V
CC PP  
– Synchronized with 33 MHz PCI clock  
BYTE PROGRAMMING TIME  
– Single Byte Mode: 10µs (typical)  
– Quadruple Byte Mode: 2.5µs (typical)  
50 MEMORY BLOCKS  
4
5
4
LAD0-  
LAD3  
ID0-ID3  
GPI0-  
GPI4  
WP  
– 1 Boot Block  
– 18 Parameter and 31 Main Blocks  
PROGRAM/ERASE CONTROLLER  
LFRAME  
CLK  
IC  
TBL  
M50LPW116  
– Embedded Byte Program and Block/Chip  
Erase algorithms  
– Status Register Bits  
RP  
PROGRAM and ERASE SUSPEND  
ELECTRONIC SIGNATURE  
– Manufacturer Code: 20h  
– Device Code: 30h  
INIT  
V
SS  
AI05466  
February 2003  
1/36  
This is preliminary information on a new product now in development or undergoing evaluation. Details are subject to change without notice.  

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