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M50FLW040AN5TP PDF预览

M50FLW040AN5TP

更新时间: 2024-10-01 04:18:27
品牌 Logo 应用领域
意法半导体 - STMICROELECTRONICS 闪存
页数 文件大小 规格书
64页 536K
描述
4-Mbit (5 】 64 Kbyte blocks + 3 】 16 】 4 Kbyte sectors) 3-V supply Firmware Hub / low-pin count Flash memory

M50FLW040AN5TP 数据手册

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M50FLW040A  
M50FLW040B  
4-Mbit (5 × 64 Kbyte blocks + 3 × 16 × 4 Kbyte sectors)  
3-V supply Firmware Hub / low-pin count Flash memory  
Feature summary  
Flash memory  
– Compatible with either the LPC interface or  
the FWH interface (Intel Spec rev1.1) used  
in PC BIOS applications  
PLCC32 (K)  
– 5 Signal Communication Interface  
supporting Read and Write Operations  
– 5 Additional General Purpose Inputs for  
platform design flexibility  
– Synchronized with 33MHz PCI clock  
8 blocks of 64 Kbytes  
– 5 blocks of 64 KBytes each  
– 3 blocks, subdivided into 16 uniform  
sectors of 4 KBytes each  
TSOP32 (NB)  
8 x 14mm  
Two blocks at the top and one at the bottom  
(M50FLW040A)  
One block at the top and two at the bottom  
(M50FLW040B)  
Enhanced security  
– Hardware Write Protect Pins for Block  
Protection  
TSOP40 (N)  
10 x 20mm  
– Register-based Read and Write Protection  
Supply voltage  
Program/Erase Suspend  
– V = 3 to 3.6V for Program, Erase and  
CC  
– Read other Blocks/Sectors during Program  
Suspend  
Read Operations  
– V = 12V for Fast Program and Erase  
PP  
– Program other Blocks/Sectors during Erase  
Suspend  
Two interfaces  
– Auto Detection of Firmware Hub (FWH) or  
Low Pin Count (LPC) Memory Cycles for  
Embedded Operation with PC Chipsets  
Electronic signature  
– Manufacturer Code: 20h  
– Device Code (M50FLW040A): 08h  
– Device Code (M50FLW040B): 28h  
– Address/Address Multiplexed (A/A Mux)  
Interface for programming equipment  
compatibility.  
Packages  
Programming time: 10 µs typical  
– ECOPACK® (RoHS compliant)  
Program/Erase Controller  
– Embedded Program and Erase algorithms  
– Status Register Bits  
October 2006  
Rev 6  
1/64  
www.st.com  
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