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M5-256/104-10YC

更新时间： 2024-11-12 23:13:51
品牌 Logo 应用领域
莱迪思 - LATTICE 可编程逻辑器件输入元件时钟
页数 文件大小 规格书
47页 1092K
描述
Fifth Generation MACH Architecture

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M5-256/104-10YC 技术参数

是否Rohs认证：不符合生命周期：Obsolete
零件包装代码：QFP包装说明：PLASTIC, QFP-144
针数：144Reach Compliance Code：compliant
ECCN代码：EAR99HTS代码：8542.39.00.01
风险等级：5.9Is Samacsys：N
其他特性：YES最大时钟频率：58.8 MHz
系统内可编程：YESJESD-30 代码：S-PQFP-G144
JESD-609代码：e0JTAG BST：YES
湿度敏感等级：3专用输入次数：
I/O 线路数量：104宏单元数：256
端子数量：144最高工作温度：70 °C
最低工作温度：组织：0 DEDICATED INPUTS, 104 I/O
输出函数：MACROCELL封装主体材料：PLASTIC/EPOXY
封装代码：QFP封装等效代码：QFP144,1.2SQ
封装形状：SQUARE封装形式：FLATPACK
电源：5 V可编程逻辑类型：EE PLD
传播延迟：10 ns认证状态：Not Qualified
子类别：Programmable Logic Devices最大供电电压：5.25 V
最小供电电压：4.75 V标称供电电压：5 V
表面贴装：YES技术：CMOS
温度等级：COMMERCIAL端子面层：Tin/Lead (Sn85Pb15)
端子形式：GULL WING端子节距：0.635 mm
端子位置：QUADBase Number Matches：1

M5-256/104-10YC 数据手册

 浏览型号M5-256/104-10YC的Datasheet PDF文件第2页浏览型号M5-256/104-10YC的Datasheet PDF文件第3页浏览型号M5-256/104-10YC的Datasheet PDF文件第4页浏览型号M5-256/104-10YC的Datasheet PDF文件第5页浏览型号M5-256/104-10YC的Datasheet PDF文件第6页浏览型号M5-256/104-10YC的Datasheet PDF文件第7页 
MACH 5 CPLD Family  
Fifth Generation MACH Architecture  
FEATURES  
  High logic densities and I/Os for increased logic integration  
— 128 to 512 macrocell densities  
— 68 to 256 I/Os  
  Wide selection of density and I/O combinations to support most application needs  
— 6 macrocell density options  
— 7 I/O options  
— Up to 4 I/O options per macrocell density  
— Up to 5 density & I/O options for each package  
  Performance features to fit system needs  
— 5.5 ns t Commercial, 7.5 ns t Industrial  
PD  
PD  
— 182 MHz f  
CNT  
— Four programmable power/speed settings per block  
  Flexible architecture facilitates logic design  
— Multiple levels of switch matrices allow for performance-based routing  
— 100% routability and pin-out retention  
— Synchronous and asynchronous clocking, including dual-edge clocking  
— Asynchronous product- or sum-term set or reset  
— 16 to 64 output enables  
— Functions of up to 32 product terms  
  Advanced capabilities for easy system integration  
— 3.3-V & 5-V JEDEC-compliant operations  
— IEEE 1149.1 compliant for boundary scan testing  
— 3.3-V & 5-V in-system programmable via IEEE 1149.1 Boundary Scan Test Access Port  
— PCI compliant (-5/-6/-7/-10/-12 speed grades)  
— Safe for mixed supply voltage system design  
— Bus-Friendly™ Inputs & I/Os  
— Individual output slew rate control  
— Hot socketing  
— Programmable security bit  
2
  Advanced E CMOS process provides high performance, cost effective solutions  
  Supported by ispDesignEXPERT™ softw are for rapid logic development  
— Supports HDL design methodologies with results optimized for MACH 5 devices  
— Flexibility to adapt to user requirements  
— Software partnerships that ensure customer success  
  Lattice and Third-party hardw are programming support  
— LatticePRO™ software for in-system programmability support on PCs and Automated Test  
Equipment  
— Programming support on all major programmers including Data I/O, BP Microsystems, Advin,  
and System General  
Publication# 20446  
Amendment/0  
Rev: I  
Issue Date: September 2000  
1234567...47

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