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M5-192/104-10HI

更新时间： 2024-01-25 05:22:24

品牌	Logo	应用领域
莱迪思 - LATTICE		可编程逻辑输入元件时钟
页数	文件大小	规格书
47页	1092K
描述
Fifth Generation MACH Architecture

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M5-192/104-10HI 技术参数

是否Rohs认证：	不符合	生命周期：	Transferred
Reach Compliance Code：	unknown	风险等级：	5.72
Is Samacsys：	N	其他特性：	YES
最大时钟频率：	83 MHz	系统内可编程：	YES
JESD-30 代码：	S-PQFP-G144	JESD-609代码：	e0
JTAG BST：	YES	专用输入次数：
I/O 线路数量：	104	宏单元数：	192
端子数量：	144	最高工作温度：	85 °C
最低工作温度：	-40 °C	组织：	0 DEDICATED INPUTS, 104 I/O
输出函数：	MACROCELL	封装主体材料：	PLASTIC/EPOXY
封装代码：	QFP	封装等效代码：	QFP144,1.2SQ
封装形状：	SQUARE	封装形式：	FLATPACK
电源：	5 V	可编程逻辑类型：	EE PLD
传播延迟：	16 ns	认证状态：	Not Qualified
子类别：	Programmable Logic Devices	最大供电电压：	5.5 V
最小供电电压：	4.5 V	标称供电电压：	5 V
表面贴装：	YES	技术：	CMOS
温度等级：	INDUSTRIAL	端子面层：	Tin/Lead (Sn/Pb)
端子形式：	GULL WING	端子节距：	0.635 mm
端子位置：	QUAD	Base Number Matches：	1

M5-192/104-10HI 数据手册

MACH 5 CPLD Family

Fifth Generation MACH Architecture

FEATURES

High logic densities and I/Os for increased logic integration

— 128 to 512 macrocell densities

— 68 to 256 I/Os

Wide selection of density and I/O combinations to support most application needs

— 6 macrocell density options

— 7 I/O options

— Up to 4 I/O options per macrocell density

— Up to 5 density & I/O options for each package

Performance features to ﬁt system needs

— 5.5 ns t Commercial, 7.5 ns t Industrial

— 182 MHz f

CNT

— Four programmable power/speed settings per block

Flexible architecture facilitates logic design

— Multiple levels of switch matrices allow for performance-based routing

— 100% routability and pin-out retention

— Synchronous and asynchronous clocking, including dual-edge clocking

— Asynchronous product- or sum-term set or reset

— 16 to 64 output enables

— Functions of up to 32 product terms

Advanced capabilities for easy system integration

— 3.3-V & 5-V JEDEC-compliant operations

— IEEE 1149.1 compliant for boundary scan testing

— 3.3-V & 5-V in-system programmable via IEEE 1149.1 Boundary Scan Test Access Port

— PCI compliant (-5/-6/-7/-10/-12 speed grades)

— Safe for mixed supply voltage system design

— Bus-Friendly™ Inputs & I/Os

— Individual output slew rate control

— Hot socketing

— Programmable security bit

Advanced E CMOS process provides high performance, cost effective solutions

Supported by ispDesignEXPERT™ softw are for rapid logic development

— Supports HDL design methodologies with results optimized for MACH 5 devices

— Flexibility to adapt to user requirements

— Software partnerships that ensure customer success

Lattice and Third-party hardw are programming support

— LatticePRO™ software for in-system programmability support on PCs and Automated Test

Equipment

— Programming support on all major programmers including Data I/O, BP Microsystems, Advin,

and System General

Publication# 20446

Amendment/0

Rev: I

Issue Date: September 2000

12 3 4 5 6 7...47

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M5-192/104-10VC	LATTICE	Fifth Generation MACH Architecture	获取价格
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M5-192/104-10YC	LATTICE	Fifth Generation MACH Architecture	获取价格
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