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M4A5-64/32-7VI PDF预览

M4A5-64/32-7VI

更新时间: 2024-10-27 22:46:43
品牌 Logo 应用领域
莱迪思 - LATTICE 可编程逻辑器件输入元件时钟
页数 文件大小 规格书
62页 1140K
描述
High Performance E 2 CMOS In-System Programmable Logic

M4A5-64/32-7VI 技术参数

是否无铅: 含铅是否Rohs认证: 不符合
生命周期:Obsolete零件包装代码:QFP
包装说明:1 MM HEIGHT, TQFP-44针数:44
Reach Compliance Code:not_compliantHTS代码:8542.39.00.01
风险等级:5.62其他特性:YES
最大时钟频率:76.9 MHz系统内可编程:YES
JESD-30 代码:S-PQFP-G44JESD-609代码:e0
JTAG BST:YES长度:10 mm
湿度敏感等级:3专用输入次数:
I/O 线路数量:32宏单元数:64
端子数量:44最高工作温度:85 °C
最低工作温度:-40 °C组织:0 DEDICATED INPUTS, 32 I/O
输出函数:MACROCELL封装主体材料:PLASTIC/EPOXY
封装代码:TQFP封装等效代码:TQFP44,.47SQ,32
封装形状:SQUARE封装形式:FLATPACK, THIN PROFILE
峰值回流温度(摄氏度):240电源:5 V
可编程逻辑类型:EE PLD传播延迟:7.5 ns
认证状态:Not Qualified座面最大高度:1.2 mm
子类别:Programmable Logic Devices最大供电电压:5.5 V
最小供电电压:4.5 V标称供电电压:5 V
表面贴装:YES技术:CMOS
温度等级:INDUSTRIAL端子面层:Tin/Lead (Sn85Pb15)
端子形式:GULL WING端子节距:0.8 mm
端子位置:QUAD处于峰值回流温度下的最长时间:30
宽度:10 mmBase Number Matches:1

M4A5-64/32-7VI 数据手册

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ispMACH4A CPLD Family  
High Performance E2CMOS®  
In-System Programmable Logic  
FEATURES  
2
  High-performance, E CMOS 3.3-V & 5-V CPLD families  
  Flexible architecture for rapid logic designs  
TM  
— Excellent First-Time-Fit  
— SpeedLocking  
and refit feature  
TM  
performance for guaranteed fixed timing  
— Central, input and output switch matrices for 100% routability and 100% pin-out retention  
  High speed  
— 5.0ns t Commercial and 7.5ns t Industrial  
PD  
PD  
— 182MHz f  
CNT  
  32 to 512 macrocells; 32 to 768 registers  
  44 to 388 pins in PLCC, PQFP, TQFP, BGA, fpBGA and caBGA packages  
  Flexible architecture for a w ide range of design styles  
— D/T registers and latches  
— Synchronous or asynchronous mode  
— Dedicated input registers  
— Programmable polarity  
— Reset/ preset swapping  
  Advanced capabilities for easy system integration  
— 3.3-V & 5-V JEDEC-compliant operations  
— JTAG (IEEE 1149.1) compliant for boundary scan testing  
— 3.3-V & 5-V JTAG in-system programming  
— PCI compliant (-5/-55/-6/-65/-7/-10/-12 speed grades)  
— Safe for mixed supply voltage system designs  
TM  
— Programmable pull-up or Bus-Friendly inputs and I/Os  
— Hot-socketing  
— Programmable security bit  
— Individual output slew rate control  
2
  Advanced E CMOS process provides high-performance, cost-effective solutions  
TM  
  Supported by ispDesignEXPERT softw are for rapid logic development  
— Supports HDL design methodologies with results optimized for ispMACH 4A  
— Flexibility to adapt to user requirements  
— Software partnerships that ensure customer success  
  Lattice and third-party hardw are programming support  
TM  
LatticePRO  
equipment  
software for in-system programmability support on PCs and automated test  
— Programming support on all major programmers including Data I/O, BP Microsystems, Advin,  
and System General  
Publication# ISPM4A Rev: D  
Amendment/0  
Issue Date: August 2000  

M4A5-64/32-7VI 替代型号

型号 品牌 替代类型 描述 数据表
M4A5-64/32-7VNI LATTICE

完全替代

EE PLD, 7.5ns, 64-Cell, CMOS, PQFP44, 1 MM HEIGHT, LEAD FREE, TQFP-44

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