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M4A5-32/32-55JC PDF预览

M4A5-32/32-55JC

更新时间: 2024-10-28 18:46:11
品牌 Logo 应用领域
莱迪思 - LATTICE 时钟输入元件可编程逻辑
页数 文件大小 规格书
62页 2620K
描述
EE PLD, 5.5ns, 32-Cell, CMOS, PQCC44,

M4A5-32/32-55JC 技术参数

是否无铅:含铅是否Rohs认证:不符合
生命周期:Obsolete零件包装代码:LCC
包装说明:PLASTIC, LCC-44针数:44
Reach Compliance Code:compliantECCN代码:EAR99
HTS代码:8542.39.00.01风险等级:5.8
Is Samacsys:N其他特性:YES
最大时钟频率:105 MHz系统内可编程:YES
JESD-30 代码:S-PQCC-J44JESD-609代码:e0
JTAG BST:YES长度:16.5862 mm
湿度敏感等级:3专用输入次数:
I/O 线路数量:32宏单元数:32
端子数量:44最高工作温度:70 °C
最低工作温度:组织:0 DEDICATED INPUTS, 32 I/O
输出函数:MACROCELL封装主体材料:PLASTIC/EPOXY
封装代码:QCCJ封装等效代码:LDCC44,.7SQ
封装形状:SQUARE封装形式:CHIP CARRIER
峰值回流温度(摄氏度):225电源:5 V
可编程逻辑类型:EE PLD传播延迟:5.5 ns
认证状态:Not Qualified座面最大高度:4.57 mm
子类别:Programmable Logic Devices最大供电电压:5.25 V
最小供电电压:4.75 V标称供电电压:5 V
表面贴装:YES技术:CMOS
温度等级:COMMERCIAL端子面层:Tin/Lead (Sn/Pb)
端子形式:J BEND端子节距:1.27 mm
端子位置:QUAD处于峰值回流温度下的最长时间:30
宽度:16.5862 mmBase Number Matches:1

M4A5-32/32-55JC 数据手册

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MACH 4 CPLD Family  
High Performance EE CMOS  
Programmable Logic  
FEATURES  
  High-performance, EE CMOS 3.3-V & 5-V CPLD families  
  Flexible architecture for rapid logic designs  
TM  
— Excellent First-Time-Fit  
— SpeedLocking  
and refit feature  
TM  
performance for guaranteed fixed timing  
— Central, input and output switch matrices for 100% routability and 100% pin-out retention  
  High speed  
— 5.0ns t Commercial and 7.5ns t Industrial  
PD  
PD  
— 182MHz f  
CNT  
  32 to 512 macrocells; 32 to 768 registers  
  44 to 352 pins in PLCC, PQFP, TQFP, BGA, or fpBGA packages  
  Advanced capabilities for easy system integration  
— 3.3-V & 5-V JEDEC-compliant operations  
— JTAG (IEEE 1149.1) compliant for boundary scan testing  
— 3.3-V & 5-V JTAG in-system programming  
— PCI compliant (-5/-55/-6/-65/-7/-10/-12 speed grades)  
— Safe for mixed supply voltage system designs  
TM  
— Programmable pull-up or Bus-Friendly inputs and I/Os  
— Hot-socketing  
— Programmable security bit  
— Individual output slew rate control  
  Flexible architecture for a w ide range of design styles  
— D/T registers and latches  
— Synchronous or asynchronous mode  
— Dedicated input registers  
— Programmable polarity  
— Reset/ preset swapping  
  Advanced EE CMOS process provides high-performance, cost-effective solutions  
TM  
  Supported by Vantis DesignDirect  
softw are for rapid logic development  
— Supports HDL design methodologies with results optimized for Vantis  
— Flexibility to adapt to user requirements  
— Software partnerships that ensure customer success  
  Lattice/Vantis and third-party hardw are programming support  
TM  
®
Lattice/VantisPRO (formerly known as MACHPRO ) software for in-system programmability  
support on PCs and automated test equipment  
— Programming support on all major programmers including Data I/O, BP Microsystems, Advin,  
and System General  
Publication# 1 7466  
Amendment/0  
Rev: J  
Issue Date: May 1 999  

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