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M4A5-128/64-7VI PDF预览

M4A5-128/64-7VI

更新时间: 2024-10-28 22:15:39
品牌 Logo 应用领域
莱迪思 - LATTICE 可编程逻辑输入元件时钟
页数 文件大小 规格书
62页 1140K
描述
High Performance E 2 CMOS In-System Programmable Logic

M4A5-128/64-7VI 技术参数

是否无铅: 含铅是否Rohs认证: 不符合
生命周期:Obsolete包装说明:TQFP-100
Reach Compliance Code:not_compliantECCN代码:EAR99
HTS代码:8542.39.00.01风险等级:5.53
其他特性:YES最大时钟频率:76.9 MHz
系统内可编程:YESJESD-30 代码:S-PQFP-G100
JESD-609代码:e0JTAG BST:YES
长度:14 mm湿度敏感等级:3
专用输入次数:2I/O 线路数量:64
宏单元数:128端子数量:100
最高工作温度:85 °C最低工作温度:-40 °C
组织:2 DEDICATED INPUTS, 64 I/O输出函数:MACROCELL
封装主体材料:PLASTIC/EPOXY封装代码:LFQFP
封装等效代码:QFP100,.7X.9封装形状:SQUARE
封装形式:FLATPACK, LOW PROFILE, FINE PITCH峰值回流温度(摄氏度):240
电源:5 V可编程逻辑类型:EE PLD
传播延迟:7.5 ns认证状态:Not Qualified
座面最大高度:1.6 mm子类别:Programmable Logic Devices
最大供电电压:5.5 V最小供电电压:4.5 V
标称供电电压:5 V表面贴装:YES
技术:CMOS温度等级:INDUSTRIAL
端子面层:Tin/Lead (Sn/Pb)端子形式:GULL WING
端子节距:0.5 mm端子位置:QUAD
处于峰值回流温度下的最长时间:30宽度:14 mm
Base Number Matches:1

M4A5-128/64-7VI 数据手册

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ispMACH4A CPLD Family  
High Performance E2CMOS®  
In-System Programmable Logic  
FEATURES  
2
  High-performance, E CMOS 3.3-V & 5-V CPLD families  
  Flexible architecture for rapid logic designs  
TM  
— Excellent First-Time-Fit  
— SpeedLocking  
and refit feature  
TM  
performance for guaranteed fixed timing  
— Central, input and output switch matrices for 100% routability and 100% pin-out retention  
  High speed  
— 5.0ns t Commercial and 7.5ns t Industrial  
PD  
PD  
— 182MHz f  
CNT  
  32 to 512 macrocells; 32 to 768 registers  
  44 to 388 pins in PLCC, PQFP, TQFP, BGA, fpBGA and caBGA packages  
  Flexible architecture for a w ide range of design styles  
— D/T registers and latches  
— Synchronous or asynchronous mode  
— Dedicated input registers  
— Programmable polarity  
— Reset/ preset swapping  
  Advanced capabilities for easy system integration  
— 3.3-V & 5-V JEDEC-compliant operations  
— JTAG (IEEE 1149.1) compliant for boundary scan testing  
— 3.3-V & 5-V JTAG in-system programming  
— PCI compliant (-5/-55/-6/-65/-7/-10/-12 speed grades)  
— Safe for mixed supply voltage system designs  
TM  
— Programmable pull-up or Bus-Friendly inputs and I/Os  
— Hot-socketing  
— Programmable security bit  
— Individual output slew rate control  
2
  Advanced E CMOS process provides high-performance, cost-effective solutions  
TM  
  Supported by ispDesignEXPERT softw are for rapid logic development  
— Supports HDL design methodologies with results optimized for ispMACH 4A  
— Flexibility to adapt to user requirements  
— Software partnerships that ensure customer success  
  Lattice and third-party hardw are programming support  
TM  
LatticePRO  
equipment  
software for in-system programmability support on PCs and automated test  
— Programming support on all major programmers including Data I/O, BP Microsystems, Advin,  
and System General  
Publication# ISPM4A Rev: D  
Amendment/0  
Issue Date: August 2000  

M4A5-128/64-7VI 替代型号

型号 品牌 替代类型 描述 数据表
M4A5-128/64-7VNI LATTICE

完全替代

EE PLD, 7.5ns, 128-Cell, CMOS, PQFP100, LEAD FREE, TQFP-100

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