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M466S1723AT2-C10 PDF预览

M466S1723AT2-C10

更新时间: 2024-11-11 20:10:47
品牌 Logo 应用领域
三星 - SAMSUNG 时钟动态存储器内存集成电路
页数 文件大小 规格书
9页 120K
描述
Synchronous DRAM Module, 16MX64, 7ns, CMOS, SODIMM-144

M466S1723AT2-C10 技术参数

是否Rohs认证: 不符合生命周期:Obsolete
零件包装代码:MODULE包装说明:DIMM, DIMM144,32
针数:144Reach Compliance Code:compliant
ECCN代码:EAR99HTS代码:8542.32.00.32
风险等级:5.92访问模式:FOUR BANK PAGE BURST
最长访问时间:7 ns其他特性:AUTO/SELF REFRESH
最大时钟频率 (fCLK):100 MHzI/O 类型:COMMON
JESD-30 代码:R-XDMA-N144内存密度:1073741824 bit
内存集成电路类型:SYNCHRONOUS DRAM MODULE内存宽度:64
功能数量:1端口数量:1
端子数量:144字数:16777216 words
字数代码:16000000工作模式:SYNCHRONOUS
最高工作温度:70 °C最低工作温度:
组织:16MX64输出特性:3-STATE
封装主体材料:UNSPECIFIED封装代码:DIMM
封装等效代码:DIMM144,32封装形状:RECTANGULAR
封装形式:MICROELECTRONIC ASSEMBLY电源:3.3 V
认证状态:Not Qualified刷新周期:4096
自我刷新:YES最大待机电流:0.008 A
子类别:DRAMs最大压摆率:1.68 mA
最大供电电压 (Vsup):3.6 V最小供电电压 (Vsup):3 V
标称供电电压 (Vsup):3.3 V表面贴装:NO
技术:CMOS温度等级:COMMERCIAL
端子形式:NO LEAD端子节距:0.8 mm
端子位置:DUALBase Number Matches:1

M466S1723AT2-C10 数据手册

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M466S1723AT2  
PC66 SODIMM  
M466S1723AT2 SDRAM SODIMM  
16Mx64 SDRAM SODIMM based on 16Mx8, 4Banks, 4K Refresh, 3.3V Synchronous DRAMs with SPD  
GENERAL DESCRIPTION  
FEATURE  
The Samsung M466S1723AT2 is a 16M bit x 64 Synchronous  
Dynamic RAM high density memory module. The Samsung  
M466S1723AT2 consists of eight CMOS 16M x 8 bit with  
4banks Synchronous DRAMs in TSOP-II 400mil package and a  
2K EEPROM in 8-pin TSSOP package on a 144-pin glass-epoxy  
substrate. Two 0.1uF decoupling capacitors are mounted on the  
printed circuit board in parallel for each SDRAM. The  
M466S1723AT2 is a Small Outline Dual In-line Memory Module  
and is intended for mounting into 144-pin edge connector sock-  
ets.  
• Performance range  
Part No.  
Max Freq. (Speed)  
M466S1723AT2-L10/C10  
66MHz (@ CL=2 & CL=3)  
• Burst mode operation  
• Auto & self refresh capability (4096 Cycles/64ms)  
• LVTTL compatible inputs and outputs  
• Single 3.3V ± 0.3V power supply  
• MRS cycle with address key programs  
Latency (Access from column address)  
Burst length (1, 2, 4, 8 & Full page)  
Synchronous design allows precise cycle control with the use of  
system clock. I/O transactions are possible on every clock cycle.  
Range of operating frequencies, programmable latencies allows  
the same device to be useful for a variety of high bandwidth,  
high performance memory system applications.  
Data scramble (Sequential & Interleave)  
• All inputs are sampled at the positive going edge of the  
system clock  
• Serial presence detect with EEPROM  
• PCB : Height (1,150mil), double sided component  
PIN CONFIGURATIONS (Front side/back side)  
PIN NAMES  
Pin Front Pin Back Pin Front Pin Back Pin Front Pin Back  
Pin Name  
A0 ~ A11  
Function  
Address input (Multiplexed)  
Select bank  
1
3
VSS  
DQ0  
DQ1  
DQ2  
2
4
6
8
VSS  
51 DQ14 52 DQ46 95 DQ21 96 DQ53  
BA0 ~ BA1  
DQ32 53 DQ15 54 DQ47 97 DQ22 98 DQ54  
DQ0 ~ DQ63 Data input/output  
CLK0 ~ CLK1 Clock input  
5
DQ33 55  
DQ34 57  
VSS  
NC  
NC  
56  
58  
60  
VSS  
99 DQ23 100 DQ55  
7
NC 101  
NC 103  
105  
VDD  
A6  
102 VDD  
104 A7  
9
DQ3 10 DQ35 59  
12  
CKE0  
CS0  
RAS  
CAS  
WE  
Clock enable input  
Chip select input  
Row address strobe  
Column address strobe  
Write enable  
11  
VDD  
VDD  
A8  
106 BA0  
108 VSS  
110 BA1  
13 DQ4 14 DQ36  
15 DQ5 16 DQ37  
107  
VSS  
A9  
Voltage Key  
109  
17 DQ6 18 DQ38 61 CLK0 62 CKE0 111 A10/AP 112 A11  
19 DQ7 20 DQ39 63 64 VDD 113 114 VDD  
21 22 65 RAS 66 CAS 115 DQM2 116 DQM6  
23 DQM0 24 DQM4 67 WE 68 *CKE1 117 DQM3 118 DQM7  
25 DQM1 26 DQM5 69 CS0 70 *A12 119 120 VSS  
71 *CS1 72 *A13 121 DQ24 122 DQ56  
VDD  
VDD  
DQM0 ~ 7  
VDD  
DQM  
VSS  
VSS  
Power supply (3.3V)  
Ground  
VSS  
VSS  
27  
29  
31  
33  
35  
VDD  
A0  
28  
30  
32  
34  
36  
VDD  
A3  
SDA  
SCL  
DU  
Serial data I/O  
Serial clock  
73  
75  
77  
79  
DU  
VSS  
NC  
74 CLK1 123 DQ25 124 DQ57  
A1  
A4  
76  
78  
80  
82  
VSS 125 DQ26 126 DQ58  
NC 127 DQ27 128 DQ59  
Don¢t use  
A2  
A5  
NC  
No connection  
VSS  
VSS  
NC  
NC 129  
VDD  
130 VDD  
37 DQ8 38 DQ40 81  
VDD  
VDD 131 DQ28 132 DQ60  
*
These pins are not used in this module.  
39 DQ9 40 DQ41 83 DQ16 84 DQ48 133 DQ29 134 DQ61  
41 DQ10 42 DQ42 85 DQ17 86 DQ49 135 DQ30 136 DQ62  
43 DQ11 44 DQ43 87 DQ18 88 DQ50 137 DQ31 138 DQ63  
** These pins should be NC in the system  
which does not support SPD.  
45  
47 DQ12 48 DQ44 91  
49 DQ13 50 DQ45 93 DQ20 94 DQ52 143  
VDD  
46  
VDD  
89 DQ19 90 DQ51 139  
92 VSS 141 **SDA 142 **SCL  
144 VDD  
VSS  
140 VSS  
VSS  
VDD  
* SAMSUNG ELECTRONICS CO., Ltd. reserves the right to change products and specifications without notice.  
REV. 0.0 Aug. 1999  

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