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M4-256/128-7YC PDF预览

M4-256/128-7YC

更新时间: 2024-11-09 03:51:11
品牌 Logo 应用领域
莱迪思 - LATTICE 可编程逻辑输入元件时钟
页数 文件大小 规格书
46页 692K
描述
High Performance E 2 CMOS In-System Programmable Logic

M4-256/128-7YC 技术参数

是否Rohs认证: 不符合生命周期:Obsolete
零件包装代码:QFP包装说明:PLASTIC, QFP-208
针数:208Reach Compliance Code:unknown
ECCN代码:EAR99HTS代码:8542.39.00.01
风险等级:5.65其他特性:YES
最大时钟频率:71.4 MHz系统内可编程:YES
JESD-30 代码:S-PQFP-G208JESD-609代码:e0
JTAG BST:YES长度:28 mm
湿度敏感等级:3专用输入次数:14
I/O 线路数量:128宏单元数:256
端子数量:208最高工作温度:70 °C
最低工作温度:组织:14 DEDICATED INPUTS, 128 I/O
输出函数:MACROCELL封装主体材料:PLASTIC/EPOXY
封装代码:FQFP封装等效代码:QFP208,1.2SQ,20
封装形状:SQUARE封装形式:FLATPACK, FINE PITCH
电源:5 V可编程逻辑类型:EE PLD
传播延迟:7.5 ns认证状态:Not Qualified
座面最大高度:4.1 mm子类别:Programmable Logic Devices
最大供电电压:5.25 V最小供电电压:4.75 V
标称供电电压:5 V表面贴装:YES
技术:CMOS温度等级:COMMERCIAL
端子面层:Tin/Lead (Sn85Pb15)端子形式:GULL WING
端子节距:0.5 mm端子位置:QUAD
宽度:28 mmBase Number Matches:1

M4-256/128-7YC 数据手册

 浏览型号M4-256/128-7YC的Datasheet PDF文件第2页浏览型号M4-256/128-7YC的Datasheet PDF文件第3页浏览型号M4-256/128-7YC的Datasheet PDF文件第4页浏览型号M4-256/128-7YC的Datasheet PDF文件第5页浏览型号M4-256/128-7YC的Datasheet PDF文件第6页浏览型号M4-256/128-7YC的Datasheet PDF文件第7页 
MACH 4 CPLD Family  
High Performance E2CMOS®  
In-System Programmable Logic  
FEATURES  
2
  High-performance, E CMOS 3.3-V & 5-V CPLD families  
  Flexible architecture for rapid logic designs  
TM  
— Excellent First-Time-Fit  
— SpeedLocking  
and refit feature  
TM  
performance for guaranteed fixed timing  
— Central, input and output switch matrices for 100% routability and 100% pin-out retention  
  High speed  
— 7.5ns t Commercial and 10ns t Industrial  
PD  
PD  
— 111.1MHz f  
CNT  
  32 to 256 macrocells; 32 to 384 registers  
  44 to 256 pins in PLCC, PQFP, TQFP and BGA packages  
  Flexible architecture for a w ide range of design styles  
— D/T registers and latches  
— Synchronous or asynchronous mode  
— Dedicated input registers  
— Programmable polarity  
— Reset/ preset swapping  
  Advanced capabilities for easy system integration  
— 3.3-V & 5-V JEDEC-compliant operations  
— JTAG (IEEE 1149.1) compliant for boundary scan testing  
— 3.3-V & 5-V JTAG in-system programming  
— PCI compliant (-7/-10/-12 speed grades)  
— Safe for mixed supply voltage system designs  
TM  
— Bus-Friendly inputs and I/Os  
— Programmable security bit  
— Individual output slew rate control  
2
  Advanced E CMOS process provides high-performance, cost-effective solutions  
TM  
  Supported by ispDesignEXPERT softw are for rapid logic development  
— Supports HDL design methodologies with results optimized for MACH 4  
— Flexibility to adapt to user requirements  
— Software partnerships that ensure customer success  
  Lattice and third-party hardw are programming support  
TM  
LatticePRO  
equipment  
software for in-system programmability support on PCs and automated test  
— Programming support on all major programmers including Data I/O, BP Microsystems, Advin,  
and System General  
Publication# 1 7466  
Amendment/0  
Rev: M  
Issue Date: March 2000  

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