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M38510/32502BRA

更新时间： 2024-11-17 11:06:39
品牌 Logo 应用领域
德州仪器 - TI 驱动锁存器总线驱动器总线收发器
页数 文件大小 规格书
24页 638K
描述
具有三态输出的八路 D 类透明锁存器 | J | 20 | -55 to 125

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M38510/32502BRA 数据手册

 浏览型号M38510/32502BRA的Datasheet PDF文件第2页浏览型号M38510/32502BRA的Datasheet PDF文件第3页浏览型号M38510/32502BRA的Datasheet PDF文件第4页浏览型号M38510/32502BRA的Datasheet PDF文件第5页浏览型号M38510/32502BRA的Datasheet PDF文件第6页浏览型号M38510/32502BRA的Datasheet PDF文件第7页 
SN54LS373, SN54LS374, SN54S373, SN54S374,  
SN74LS373, SN74LS374, SN74S373, SN74S374  
OCTAL D-TYPE TRANSPARENT LATCHES AND EDGE-TRIGGERED FLIP-FLOPS  
SDLS165B – OCTOBER 1975 – REVISED AUGUST 2002  
SN54LS373, SN54LS374, SN54S373,  
SN54S374 . . . J OR W PACKAGE  
SN74LS373, SN74S374 . . . DW, N, OR NS PACKAGE  
Choice of Eight Latches or Eight D-Type  
Flip-Flops in a Single Package  
3-State Bus-Driving Outputs  
Full Parallel Access for Loading  
Buffered Control Inputs  
SN74LS374 . . . DB, DW, N, OR NS PACKAGE  
SN74S373 . . . DW OR N PACKAGE  
(TOP VIEW)  
1
2
3
4
5
6
7
8
9
10  
20  
19  
18  
17  
16  
15  
14  
13  
12  
11  
OC  
1Q  
V
CC  
Clock-Enable Input Has Hysteresis to  
Improve Noise Rejection (’S373 and ’S374)  
8Q  
8D  
7D  
7Q  
6Q  
6D  
5D  
5Q  
1D  
P-N-P Inputs Reduce DC Loading on Data  
Lines (’S373 and ’S374)  
2D  
2Q  
3Q  
description  
3D  
These 8-bit registers feature 3-state outputs  
designed specifically for driving highly capacitive  
or relatively low-impedance loads. The  
4D  
4Q  
†
GND  
C
high-impedance  
3-state  
and  
increased  
†
Cfor’LS373and’S373;CLKfor’LS374and’S374.  
high-logic-level drive provide these registers with  
the capability of being connected directly to and  
driving the bus lines in a bus-organized system  
without need for interface or pullup components.  
These devices are particularly attractive for  
implementing buffer registers, I/O ports,  
bidirectional bus drivers, and working registers.  
SN54LS373, SN54LS374, SN54S373,  
SN54S374 . . . FK PACKAGE  
(TOP VIEW)  
3
2
1
20 19  
18  
The eight latches of the ’LS373 and ’S373 are  
transparent D-type latches, meaning that while  
the enable (C or CLK) input is high, the Q outputs  
follow the data (D) inputs. When C or CLK is taken  
low, the output is latched at the level of the data  
that was set up.  
8D  
7D  
7Q  
6Q  
6D  
2D  
2Q  
3Q  
3D  
4D  
4
5
6
7
8
17  
16  
15  
14  
9 10 11 12 13  
The eight flip-flops of the ’LS374 and ’S374 are  
edge-triggered D-type flip-flops. On the positive  
transition of the clock, the Q outputs are set to the  
logic states that were set up at the D inputs.  
†
Cfor’LS373and’S373;CLKfor’LS374and’S374.  
Schmitt-trigger buffered inputs at the enable/clock lines of the ’S373 and ’S374 devices simplify system design  
as ac and dc noise rejection is improved by typically 400 mV due to the input hysteresis. A buffered  
output-control (OC) input can be used to place the eight outputs in either a normal logic state (high or low logic  
levels) or the high-impedance state. In the high-impedance state, the outputs neither load nor drive the bus lines  
significantly.  
OC does not affect the internal operation of the latches or flip-flops. That is, the old data can be retained or new  
data can be entered, even while the outputs are off.  
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of  
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.  
Copyright 2002, Texas Instruments Incorporated  
On products compliant to MIL-PRF-38535, all parameters are tested  
PRODUCTION DATA information is current as of publication date.  
Products conform to specifications per the terms of Texas Instruments  
standard warranty. Production processing does not necessarily include  
unless otherwise noted. On all other products, production  
testing of all parameters.  
processing does not necessarily include testing of all parameters.  
1
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265  
1234567...24

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M38510/32502BRA 替代型号

型号 品牌 替代类型 描述 数据表
SNJ54LS373J TI

完全替代

 OCTAL D-TYPE TRANSPARENT LATCHES AND EDGE-TRIGGERED FLIP-FLOPS

与M38510/32502BRA相关器件

型号 品牌 获取价格 描述 数据表
M38510/32502BSA TI

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 		具有三态输出的八路 D 类透明锁存器 | W | 20 | -55 to 125
M38510/32502BSX ACTEL

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 		LS SERIES, 8-BIT DRIVER, TRUE OUTPUT, CDFP20, CERAMIC, DFP-20
M38510/32502SRA TI

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 		具有三态输出的八路 D 类透明锁存器 | J | 20 | -55 to 125
M38510/32502SSA TI

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 		具有三态输出的八路 D 类透明锁存器 | W | 20 | -55 to 125
M38510/32502SSX ACTEL

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 		Bus Driver, LS Series, 1-Func, 8-Bit, True Output, TTL, CDFP20, CERAMIC, DFP-20
M38510/32503B2A TI

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 		具有三态输出的八路边沿触发式 D 型触发器 | FK | 20 | -55 to 125
M38510/32503B2X ACTEL

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 		LS SERIES, 8-BIT DRIVER, TRUE OUTPUT, CQCC20, CERAMIC, LCC-20
M38510/32503BRA TI

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 		具有三态输出的八路边沿触发式 D 型触发器 | J | 20 | -55 to 125
M38510/32503BRX ACTEL

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 		Bus Driver, LS Series, 1-Func, 8-Bit, True Output, TTL, CDIP20, CERAMIC, DIP-20
M38510/32503BSA TI

获取价格

 		具有三态输出的八路边沿触发式 D 型触发器 | W | 20 | -55 to 125

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