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M36W432BG70ZA1 PDF预览

M36W432BG70ZA1

更新时间: 2024-11-20 18:56:59
品牌 Logo 应用领域
意法半导体 - STMICROELECTRONICS 静态存储器内存集成电路
页数 文件大小 规格书
66页 439K
描述
SPECIALTY MEMORY CIRCUIT, PBGA66, 12 X 8 MM, 0.80 MM PITCH, LFBGA-66

M36W432BG70ZA1 技术参数

是否Rohs认证: 不符合生命周期:Obsolete
零件包装代码:BGA包装说明:12 X 8 MM, 0.80 MM PITCH, LFBGA-66
针数:66Reach Compliance Code:not_compliant
HTS代码:8542.32.00.71风险等级:5.71
最长访问时间:70 ns其他特性:STATIC RAM ORGANISED AS 256K X 16
JESD-30 代码:R-PBGA-B66JESD-609代码:e0
长度:12 mm内存密度:33554432 bit
内存集成电路类型:MEMORY CIRCUIT内存宽度:16
混合内存类型:FLASH+SRAM功能数量:1
端子数量:66字数:2097152 words
字数代码:2000000工作模式:ASYNCHRONOUS
最高工作温度:70 °C最低工作温度:
组织:2MX16封装主体材料:PLASTIC/EPOXY
封装代码:LFBGA封装等效代码:BGA66,8X12,32
封装形状:RECTANGULAR封装形式:GRID ARRAY, LOW PROFILE, FINE PITCH
峰值回流温度(摄氏度):NOT SPECIFIED电源:3 V
认证状态:Not Qualified座面最大高度:1.4 mm
最大待机电流:0.00001 A子类别:Other Memory ICs
最大压摆率:0.02 mA最大供电电压 (Vsup):3.3 V
最小供电电压 (Vsup):2.7 V标称供电电压 (Vsup):3 V
表面贴装:YES技术:CMOS
温度等级:COMMERCIAL端子面层:Tin/Lead (Sn/Pb)
端子形式:BALL端子节距:0.8 mm
端子位置:BOTTOM处于峰值回流温度下的最长时间:NOT SPECIFIED
宽度:8 mmBase Number Matches:1

M36W432BG70ZA1 数据手册

 浏览型号M36W432BG70ZA1的Datasheet PDF文件第2页浏览型号M36W432BG70ZA1的Datasheet PDF文件第3页浏览型号M36W432BG70ZA1的Datasheet PDF文件第4页浏览型号M36W432BG70ZA1的Datasheet PDF文件第5页浏览型号M36W432BG70ZA1的Datasheet PDF文件第6页浏览型号M36W432BG70ZA1的Datasheet PDF文件第7页 
M36W432TG  
M36W432BG  
32 Mbit (2Mb x16, Boot Block) Flash Memory  
and 4 Mbit (256Kb x16) SRAM, Multiple Memory Product  
PRELIMINARY DATA  
FEATURES SUMMARY  
MULTIPLE MEMORY PRODUCT  
SRAM  
4 Mbit (256Kb x 16)  
– 32 Mbit (2Mb x 16), Boot Block, Flash Memory  
– 4 Mbit (256Kb x 16) SRAM Memory  
SUPPLY VOLTAGE  
ACCESS TIME: 70ns  
LOW V  
DATA RETENTION: 1.5V  
DDS  
– V  
– V  
– V  
= 2.7V to 3.3V  
DDF  
DDS  
PPF  
POWER DOWN FEATURES USING TWO  
CHIP ENABLE INPUTS  
= V  
= 2.7V to 3.3V  
DDQF  
= 12V for Fast Program (optional)  
Figure 1. Package  
ACCESS TIME: 70ns, 85ns  
LOW POWER CONSUMPTION  
ELECTRONIC SIGNATURE  
– Manufacturer Code: 20h  
– Top Device Code, M36W432TG: 88BAh  
– Bottom Device Code, M36W432BG: 88BBh  
FBGA  
FLASH MEMORY  
MEMORY BLOCKS  
– Parameter Blocks (Top or Bottom Location)  
– Main Blocks  
Stacked LFBGA66 (ZA)  
12 x 8 mm  
PROGRAMMING TIME  
– 10µs typical  
– Double Word Programming Option  
– Quadruple Word Programming Option  
BLOCK LOCKING  
– All blocks locked at Power up  
– Any combination of blocks can be locked  
– WP for Block Lock-Down  
F
AUTOMATIC STANDBY MODE  
PROGRAM and ERASE SUSPEND  
100,000 PROGRAM/ERASE CYCLES per  
BLOCK  
COMMON FLASH INTERFACE  
SECURITY  
– 128 bit user programmable OTP cells  
– 64 bit unique device identifier  
November 2002  
1/66  
This is preliminary information on a new product now in development or undergoing evaluation. Details are subject to change without notice.  

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IC,MIXED MEMORY,FLASH+SRAM,CMOS,BGA,66PIN,PLASTIC