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M30L0R8000B0ZAQE PDF预览

M30L0R8000B0ZAQE

更新时间: 2024-10-27 22:05:47
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意法半导体 - STMICROELECTRONICS /
页数 文件大小 规格书
83页 1370K
描述
256 Mbit (16Mb x16, Multiple Bank, Multi-Level, Burst) 1.8V Supply Flash Memory

M30L0R8000B0ZAQE 数据手册

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M30L0R8000T0  
M30L0R8000B0  
256 Mbit (16Mb x16, Multiple Bank, Multi-Level, Burst)  
1.8V Supply Flash Memory  
FEATURES SUMMARY  
SUPPLY VOLTAGE  
Figure 1. Package  
V
read  
= 1.7V to 2.0V for program, erase and  
DD  
V
V
= 1.7V to 2.0V for I/O Buffers  
DDQ  
= 9V for fast program (12V tolerant)  
PP  
SYNCHRONOUS / ASYNCHRONOUS READ  
Synchronous Burst Read mode:  
54MHz  
FBGA  
Asynchronous Page Read mode  
Random Access: 85ns  
SYNCHRONOUS BURST READ SUSPEND  
PROGRAMMING TIME  
10µs typical Word program time using  
Buffer Enhanced Factory Program  
command  
TFBGA88 (ZAQ) 8 x 10mm  
MEMORY ORGANIZATION  
Multiple Bank Memory Array: 16 Mbit  
Banks  
Parameter Blocks (Top or Bottom  
location)  
ELECTRONIC SIGNATURE  
Manufacturer Code: 20h  
Top Device Code,  
M30L0R8000T0: 880Dh.  
DUAL OPERATIONS  
program/erase in one Bank while read in  
others  
Bottom Device Code,  
M30L0R8000B0: 880Eh.  
No delay between read and write  
operations  
PACKAGE  
BLOCK LOCKING  
Compliant with Lead-Free Soldering  
Processes  
All blocks locked at power-up  
Any combination of blocks can be locked  
with zero latency  
Lead-Free Versions  
WP for Block Lock-Down  
Absolute Write Protection with V = V  
PP  
SS  
SECURITY  
64 bit unique device number  
2112 bit user programmable OTP Cells  
COMMON FLASH INTERFACE (CFI)  
100,000 PROGRAM/ERASE CYCLES per  
BLOCK  
May 2005  
1/83  

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