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M30L0R7000T0ZAQF

更新时间： 2024-10-27 22:07:47

品牌	Logo	应用领域
意法半导体 - STMICROELECTRONICS		/
页数	文件大小	规格书
83页	1327K
描述
128 Mbit (8Mb x16, Multiple Bank, Multi-Level, Burst), 1.8V Supply Flash Memory

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数据手册

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M30L0R7000T0ZAQF 数据手册

M30L0R7000T0

M30L0R7000B0

128 Mbit (8Mb x16, Multiple Bank, Multi-Level, Burst)

1.8V Supply Flash Memory

FEATURES SUMMARY

■

SUPPLY VOLTAGE

Figure 1. Package

–

V_DD= 1.7V to 2.0V for program, erase and

read

–

V_DDQ= 1.7V to 2.0V for I/O Buffers

V_PP= 9V for fast program (12V tolerant)

■

SYNCHRONOUS / ASYNCHRONOUS READ

FBGA

–

Synchronous Burst Read mode: 54MHz

Asynchronous Page Read mode

Random Access: 85ns

■

SYNCHRONOUS BURST READ SUSPEND

PROGRAMMING TIME

–

10µs typical Word program time using

Buffer Program

TFBGA88 (ZAQ)

8 x 10mm

■

MEMORY ORGANIZATION

–

Multiple Bank Memory Array: 8 Mbit

Banks

–

Parameter Blocks (Top or Bottom

location)

DUAL OPERATIONS

■

ELECTRONIC SIGNATURE

–

program/erase in one Bank while read in

others

–

Manufacturer Code: 20h

Top Device Code: 88C4h.

Bottom Device Code: 88C5h

–

No delay between read and write

operations

■ PACKAGE

BLOCK LOCKING

–

All blocks locked at power-up

Any combination of blocks can be locked

with zero latency

WP for Block Lock-Down

Absolute Write Protection with V_PP= V_SS

– Compliant with Lead-Free Soldering

Processes

– Lead-Free Versions

–

■

SECURITY

–

64 bit unique device number

2112 bit user programmable OTP Cells

■

COMMON FLASH INTERFACE (CFI)

100,000 PROGRAM/ERASE CYCLES per

BLOCK

December 2004

1/83

12 3 4 5 6 7...83

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