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M29F200B-70M1R PDF预览

M29F200B-70M1R

更新时间: 2024-11-09 22:55:59
品牌 Logo 应用领域
意法半导体 - STMICROELECTRONICS 闪存存储内存集成电路光电二极管
页数 文件大小 规格书
33页 227K
描述
2 Mbit 256Kb x8 or 128Kb x16, Boot Block Single Supply Flash Memory

M29F200B-70M1R 技术参数

生命周期:Obsolete零件包装代码:SOIC
包装说明:0.525 INCH, PLASTIC, SO-44针数:44
Reach Compliance Code:unknownECCN代码:EAR99
HTS代码:8542.32.00.51风险等级:5.14
Is Samacsys:N最长访问时间:70 ns
其他特性:BOTTOM BOOT BLOCK备用内存宽度:8
启动块:BOTTOMJESD-30 代码:R-PDSO-G44
长度:28.2 mm内存密度:2097152 bit
内存集成电路类型:FLASH内存宽度:16
功能数量:1端子数量:44
字数:131072 words字数代码:128000
工作模式:ASYNCHRONOUS最高工作温度:70 °C
最低工作温度:组织:128KX16
封装主体材料:PLASTIC/EPOXY封装代码:SOP
封装形状:RECTANGULAR封装形式:SMALL OUTLINE
并行/串行:PARALLEL编程电压:5 V
认证状态:Not Qualified座面最大高度:2.62 mm
最大供电电压 (Vsup):5.5 V最小供电电压 (Vsup):4.5 V
标称供电电压 (Vsup):5 V表面贴装:YES
技术:CMOS温度等级:COMMERCIAL
端子形式:GULL WING端子节距:1.27 mm
端子位置:DUAL类型:NOR TYPE
宽度:13.3 mmBase Number Matches:1

M29F200B-70M1R 数据手册

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M29F200T  
M29F200B  
2 Mbit (256Kb x8 or 128Kb x16, Boot Block)  
Single Supply Flash Memory  
5V±10% SUPPLYVOLTAGEfor PROGRAM,  
ERASE and READ OPERATIONS  
FASTACCESS TIME: 55ns  
FAST PROGRAMMING TIME  
– 10 s by Byte / 16 s by Word typical  
µ
µ
44  
PROGRAM/ERASE CONTROLLER (P/E.C.)  
– Program Byte-by-Byte or Word-by-Word  
– Status Register bits and Ready/Busy Output  
MEMORY BLOCKS  
– Boot Block (Top or Bottom location)  
– Parameterand Main blocks  
1
TSOP48 (N)  
12 x 20 mm  
SO44 (M)  
BLOCK, MULTI-BLOCK and CHIP ERASE  
MULTI-BLOCKPROTECTION/TEMPORARY  
UNPROTECTION MODES  
ERASE SUSPEND and RESUME MODES  
– Read and Program another Block during  
Erase Suspend  
Figure 1. Logic Diagram  
LOW POWER CONSUMPTION  
– Stand-byand AutomaticStand-by  
100,000 PROGRAM/ERASE CYCLES per  
BLOCK  
V
CC  
20 YEARSDATARETENTION  
– Defectivity below 1ppm/year  
ELECTRONIC SIGNATURE  
– ManufacturerCode: 0020h  
– Device Code, M29F200T: 00D3h  
– Device Code, M29F200B: 00D4h  
17  
15  
A0-A16  
DQ0-DQ14  
W
DQ15A–1  
BYTE  
RB  
M29F200T  
M29F200B  
E
G
DESCRIPTION  
The M29F200 is a non-volatile memory that may  
be erased electrically at the block or chiplevel and  
programmedin-systemona Byte-by-Byteor Word-  
by-Word basis using only a single 5V VCC supply.  
For Program and Erase operations the necessary  
high voltages are generatedinternally. The device  
can also be programmed in standard program-  
mers.  
The array matrix organisationallows each block to  
be erased and reprogrammed without affecting  
other blocks. Blocks can be protectedagainst pro-  
graming and erase on programming equipment,  
and temporarily unprotected to make changes in  
the application.  
RP  
V
SS  
AI01986  
July 1998  
1/33  

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