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M28LV64-250P6 PDF预览

M28LV64-250P6

更新时间: 2024-11-06 22:51:43
品牌 Logo 应用领域
意法半导体 - STMICROELECTRONICS 存储内存集成电路光电二极管可编程只读存储器电动程控只读存储器电可擦编程只读存储器
页数 文件大小 规格书
18页 128K
描述
64K 8K x 8 LOW VOLTAGE PARALLEL EEPROM with SOFTWARE DATA PROTECTION

M28LV64-250P6 技术参数

是否Rohs认证: 符合生命周期:Obsolete
零件包装代码:DIP包装说明:DIP, DIP28,.6
针数:28Reach Compliance Code:compliant
ECCN代码:EAR99HTS代码:8542.32.00.51
风险等级:5.84Is Samacsys:N
最长访问时间:250 ns其他特性:ENDURANCE >100000 ERASE/WRITE CYCLES; DATA RETENTION >40 YEARS; SOFTWARE DATA PROTECTION
命令用户界面:NO数据轮询:YES
数据保留时间-最小值:40耐久性:100000 Write/Erase Cycles
JESD-30 代码:R-PDIP-T28JESD-609代码:e3
长度:36.02 mm内存密度:65536 bit
内存集成电路类型:EEPROM内存宽度:8
功能数量:1端子数量:28
字数:8192 words字数代码:8000
工作模式:ASYNCHRONOUS最高工作温度:85 °C
最低工作温度:-40 °C组织:8KX8
封装主体材料:PLASTIC/EPOXY封装代码:DIP
封装等效代码:DIP28,.6封装形状:RECTANGULAR
封装形式:IN-LINE页面大小:64 words
并行/串行:PARALLEL峰值回流温度(摄氏度):NOT SPECIFIED
电源:3/3.3 V编程电压:3 V
认证状态:Not Qualified就绪/忙碌:YES
座面最大高度:5.08 mm最大待机电流:0.00002 A
子类别:EEPROMs最大压摆率:0.01 mA
最大供电电压 (Vsup):3.6 V最小供电电压 (Vsup):2.7 V
表面贴装:NO技术:CMOS
温度等级:INDUSTRIAL端子面层:Matte Tin (Sn)
端子形式:THROUGH-HOLE端子节距:2.54 mm
端子位置:DUAL处于峰值回流温度下的最长时间:NOT SPECIFIED
切换位:YES宽度:15.24 mm
Base Number Matches:1

M28LV64-250P6 数据手册

 浏览型号M28LV64-250P6的Datasheet PDF文件第2页浏览型号M28LV64-250P6的Datasheet PDF文件第3页浏览型号M28LV64-250P6的Datasheet PDF文件第4页浏览型号M28LV64-250P6的Datasheet PDF文件第5页浏览型号M28LV64-250P6的Datasheet PDF文件第6页浏览型号M28LV64-250P6的Datasheet PDF文件第7页 
M28LV64  
64K (8K x 8) LOW VOLTAGE PARALLEL EEPROM  
with SOFTWARE DATA PROTECTION  
NOT FOR NEW DESIGN  
FAST ACCESS TIME: 200ns  
SINGLE LOW VOLTAGE OPERATION  
LOW POWER CONSUMPTION  
FAST WRITE CYCLE:  
– 64 Bytes Page Write Operation  
– Byte or Page Write Cycle: 3ms Max  
ENHANCED END OF WRITE DETECTION:  
28  
1
– Ready/BusyOpen Drain Output  
(only on the M28LV64)  
PDIP28 (P)  
PLCC32 (K)  
– Data Polling  
– Toggle Bit  
PAGE LOAD TIMER STATUS BIT  
28  
HIGH RELIABILITYSINGLE POLYSILICON,  
CMOS TECHNOLOGY:  
1
– Endurance>100,000 Erase/Write Cycles  
– Data Retention >40 Years  
SO28 (MS)  
300 mils  
TSOP28 (N)  
8 x13.4mm  
JEDEC APPROVED BYTEWIDE PIN OUT  
SOFTWARE DATA PROTECTION  
The M28LV64 is replaced by the  
M28C64-xxW  
Figure 1. Logic Diagram  
DESCRIPTION  
The M28LV64 is an 8K x 8 low power Parallel  
EEPROM fabricated with SGS-THOMSON pro-  
prietary single polysilicon CMOS technology. The  
device offers fast access time with low power dis-  
sipation and requires a 2.7V to 3.6V power supply.  
V
CC  
13  
8
A0-A12  
DQ0-DQ7  
Table 1. Signal Names  
W
E
M28LV64  
A0 - A12  
Address Input  
DQ0 - DQ7 Data Input / Output  
RB *  
G
W
Write Enable  
Chip Enable  
Output Enable  
Ready / Busy  
Supply Voltage  
Ground  
E
G
V
SS  
RB  
VCC  
VSS  
AI01538B  
Note: * RB function is only available on the M28LV64.  
May 1997  
1/18  
This is information on a product still in production but not recommended for new designs.  

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