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M27256-2F1 PDF预览

M27256-2F1

更新时间: 2024-09-27 22:46:47
品牌 Logo 应用领域
意法半导体 - STMICROELECTRONICS 可编程只读存储器电动程控只读存储器
页数 文件大小 规格书
9页 65K
描述
NMOS 256K 32K x 8 UV EPROM

M27256-2F1 技术参数

是否Rohs认证: 不符合生命周期:Obsolete
零件包装代码:DIP包装说明:WINDOWED, FRIT SEALED, CERAMIC, DIP-28
针数:28Reach Compliance Code:not_compliant
ECCN代码:EAR99HTS代码:8542.32.00.61
风险等级:5.28最长访问时间:200 ns
I/O 类型:COMMONJESD-30 代码:R-GDIP-T28
JESD-609代码:e0内存密度:262144 bit
内存集成电路类型:UVPROM内存宽度:8
功能数量:1端子数量:28
字数:32768 words字数代码:32000
工作模式:ASYNCHRONOUS最高工作温度:70 °C
最低工作温度:组织:32KX8
输出特性:3-STATE封装主体材料:CERAMIC, GLASS-SEALED
封装代码:WDIP封装等效代码:DIP28,.6
封装形状:RECTANGULAR封装形式:IN-LINE, WINDOW
并行/串行:PARALLEL峰值回流温度(摄氏度):NOT SPECIFIED
电源:5 V编程电压:12.5 V
认证状态:Not Qualified座面最大高度:5.71 mm
子类别:EPROMs最大压摆率:0.1 mA
最大供电电压 (Vsup):5.25 V最小供电电压 (Vsup):4.75 V
标称供电电压 (Vsup):5 V表面贴装:NO
技术:NMOS温度等级:COMMERCIAL
端子面层:Tin/Lead (Sn/Pb)端子形式:THROUGH-HOLE
端子节距:2.54 mm端子位置:DUAL
处于峰值回流温度下的最长时间:NOT SPECIFIED宽度:15.24 mm

M27256-2F1 数据手册

 浏览型号M27256-2F1的Datasheet PDF文件第2页浏览型号M27256-2F1的Datasheet PDF文件第3页浏览型号M27256-2F1的Datasheet PDF文件第4页浏览型号M27256-2F1的Datasheet PDF文件第5页浏览型号M27256-2F1的Datasheet PDF文件第6页浏览型号M27256-2F1的Datasheet PDF文件第7页 
M74HC51  
DUAL 2 WIDE 2 INPUT AND/OR INVERT GATE  
HIGH SPEED:  
= 11ns (TYP.) at V = 6V  
t
PD  
CC  
LOW POWER DISSIPATION:  
= 1µA(MAX.) at T =25°C  
I
CC  
A
HIGH NOISE IMMUNITY:  
= V = 28 % V (MIN.)  
V
NIH  
NIL  
CC  
DIP  
SOP  
TSSOP  
T & R  
SYMMETRICAL OUTPUT IMPEDANCE:  
|I | = I = 4mA (MIN)  
OH  
OL  
BALANCED PROPAGATION DELAYS:  
ORDER CODES  
PACKAGE  
t
t
PLH  
PHL  
TUBE  
WIDE OPERATING VOLTAGE RANGE:  
(OPR) = 2V to 6V  
V
DIP  
SOP  
M74HC51B1R  
M74HC51M1R  
CC  
M74HC51RM13TR  
M74HC51TTR  
PIN AND FUNCTION COMPATIBLE WITH  
74 SERIES 51  
TSSOP  
DESCRIPTION  
The internal circuit is composed of 3 stages (2  
INPUT) or 5 stages (3 INPUT) including buffer  
output, which enables high noise immunity and  
stable output.  
The M74HC51 is an high speed CMOS DUAL 2  
WIDE  
2
INPUT AND/OR INVERT GATE  
2
fabricated with silicon gate C MOS technology.  
It contains a 2-WIDE 2-INPUT AND/OR INVERT  
All inputs are equipped with protection circuits  
against static discharge and transient excess  
voltage.  
GATE and a 2-WIDE 3-INPUT  
INVERT GATE.  
AND/OR  
PIN CONNECTION AND IEC LOGIC SYMBOLS  
August 2001  
1/9  

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