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M27256-20F1 PDF预览

M27256-20F1

更新时间: 2024-11-15 22:30:43
品牌 Logo 应用领域
意法半导体 - STMICROELECTRONICS 可编程只读存储器电动程控只读存储器
页数 文件大小 规格书
9页 65K
描述
NMOS 256K 32K x 8 UV EPROM

M27256-20F1 数据手册

 浏览型号M27256-20F1的Datasheet PDF文件第2页浏览型号M27256-20F1的Datasheet PDF文件第3页浏览型号M27256-20F1的Datasheet PDF文件第4页浏览型号M27256-20F1的Datasheet PDF文件第5页浏览型号M27256-20F1的Datasheet PDF文件第6页浏览型号M27256-20F1的Datasheet PDF文件第7页 
M74HC51  
DUAL 2 WIDE 2 INPUT AND/OR INVERT GATE  
HIGH SPEED:  
= 11ns (TYP.) at V = 6V  
t
PD  
CC  
LOW POWER DISSIPATION:  
= 1µA(MAX.) at T =25°C  
I
CC  
A
HIGH NOISE IMMUNITY:  
= V = 28 % V (MIN.)  
V
NIH  
NIL  
CC  
DIP  
SOP  
TSSOP  
T & R  
SYMMETRICAL OUTPUT IMPEDANCE:  
|I | = I = 4mA (MIN)  
OH  
OL  
BALANCED PROPAGATION DELAYS:  
ORDER CODES  
PACKAGE  
t
t
PLH  
PHL  
TUBE  
WIDE OPERATING VOLTAGE RANGE:  
(OPR) = 2V to 6V  
V
DIP  
SOP  
M74HC51B1R  
M74HC51M1R  
CC  
M74HC51RM13TR  
M74HC51TTR  
PIN AND FUNCTION COMPATIBLE WITH  
74 SERIES 51  
TSSOP  
DESCRIPTION  
The internal circuit is composed of 3 stages (2  
INPUT) or 5 stages (3 INPUT) including buffer  
output, which enables high noise immunity and  
stable output.  
The M74HC51 is an high speed CMOS DUAL 2  
WIDE  
2
INPUT AND/OR INVERT GATE  
2
fabricated with silicon gate C MOS technology.  
It contains a 2-WIDE 2-INPUT AND/OR INVERT  
All inputs are equipped with protection circuits  
against static discharge and transient excess  
voltage.  
GATE and a 2-WIDE 3-INPUT  
INVERT GATE.  
AND/OR  
PIN CONNECTION AND IEC LOGIC SYMBOLS  
August 2001  
1/9  

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