Datasheet > M24L816512SA-55BIG

M24L816512SA-55BIG

更新时间： 2024-09-26 05:44:55

品牌	Logo	应用领域
晶豪 - ESMT		/
页数	文件大小	规格书
14页	328K
描述
8-Mbit (512K x 16) Pseudo Static RAM

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中文翻译

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数据手册

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ESMT

M24L816512SA

PSRAM

8-Mbit (512K x 16)

Pseudo Static RAM

Features

‧Advanced low-power architecture

• High speed: 55 ns, 70 ns

Byte Low Enable are disabled (BHE ,BLE HIGH), or during

• Wide voltage range: 2.7V to 3.6V

• Typical active current: 2 mA @ f = 1 MHz

• Typical active current: 11 mA @ f = f_MAX

• Low standby power

a write operation ( CE LOW and WE LOW).

Writing to the device is accomplished by taking Chip

Enable( CE LOW) and Write Enable ( WE ) input LOW. If

• Automatic power-down when deselected

Byte Low Enable (BLE ) is LOW, then data from I/O pins (I/O₀

through I/O₇) is written into the location specified on the

Functional Description

address pins(A₀through A₁₈). If Byte High Enable (BHE ) is

LOW, then data from I/O pins (I/O₈through I/O₁₅) is written

into the location specified on the address pins (A₀through

A₁₈).

The M24L816512SA is a high-performance CMOS pseudo

static RAM (PSRAM) organized as 512K words by 16 bits that

supports an asynchronous memory interface. This device

features advanced circuit design to provide ultra-low active

current. This is ideal for portable applications such as cellular

telephones. The device can be put into standby mode when

Reading from the device is accomplished by taking Chip

Enable ( CE LOW) and Output Enable ( OE ) LOW while

forcing the Write Enable ( WE ) HIGH. If Byte Low Enable

deselected ( CE HIGH or both BHE and BLE are HIGH).

The input/output pins (I/O0through I/O₁₅) are placed in a

(BLE ) is LOW, then data from the memory location specified

by the address pins will appear on I/O₀to I/O₇. If Byte High

high-impedance state when : deselected ( CE HIGH),

Enable(BHE ) is LOW, then data from memory will appear on

I/O₈toI/O₁₅. Refer to the truth table for a complete description

of read and write modes.

outputs are disabled ( OE HIGH), both Byte High Enable

and

Logic Block Diagram

Elite Semiconductor Memory Technology Inc.

Publication Date : Jun. 2009

Revision : 1.5

1/14

12 3 4 5 6 7...14

中文翻译

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与M24L816512SA-55BIG相关器件

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