Datasheet > M24L48512DA

M24L48512DA

更新时间： 2024-09-26 05:44:55

品牌	Logo	应用领域
晶豪 - ESMT		/
页数	文件大小	规格书
12页	278K
描述
4-Mbit (512K x 8) Pseudo Static RAM

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数据手册

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M24L48512DA 数据手册

ESMT

M24L48512DA

PSRAM

4-Mbit (512K x 8)

Pseudo Static RAM

Features

Enable ( WE )inputs LOW and Chip Enable Two (CE2) input

HIGH. Data on the eight I/O pins (I/O₀through I/O₁₅) is then

written into the location specified on the address pins (A₀

through A₁₈).

• Advanced low power architecture

• High speed: 55 ns, 60 ns and 70 ns

• Wide voltage range: 2.7V to 3.6V

• Typical active current: 1mA @ f = 1 MHz

• Low standby power

Reading from the device is accomplished by asserting the

Chip Enable One ( CE1) and Output Enable ( OE ) inputs LOW

while forcing Write Enable ( WE ) HIGH and Chip Enable

Two(CE2) HIGH. Under these conditions, the contents of the

memory location specified by the address pins will appear on

the I/O pins.

• Automatic power-down when deselected

Functional Description

The eight input/output pins (I/O₀through I/O₇) are placed in a

The M24L48512DA is a high-performance CMOS pseudo

static RAM (PSRAM) organized as 512K words by 8 bits. Easy

memory expansion is provided by an active LOW Chip

high-impedance state when the device is deselected CE1

HIGH or CE2 LOW), the outputs are disabled ( OE HIGH), or

Enable( CE1), an active HIGH Chip Enable (CE2), and active

during write operation ( CE1 LOW, CE2 HIGH, and WE

LOW).See the Truth Table for a complete description of read

and write modes.

LOW Output Enable ( OE ).This device has an automatic

power-down feature that reduces power consumption

dramatically when deselected. Writing to the device is

accomplished by taking Chip Enable One ( CE1) and Write

Logic Block Diagram

Elite Semiconductor Memory Technology Inc.

Publication Date : Jul. 2008

Revision : 1.1

1/12

12 3 4 5 6 7...12

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