Datasheet > M24L28256SA

M24L28256SA

更新时间： 2024-09-24 05:44:55

品牌	Logo	应用领域
晶豪 - ESMT		/
页数	文件大小	规格书
12页	243K
描述
2-Mbit (256K x 8) Pseudo Static RAM

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数据手册

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M24L28256SA 数据手册

ESMT

M24L28256SA

PSRAM

2-Mbit (256K x 8)

Pseudo Static RAM

Features

the device is accomplished by asserting Chip Enable ( CE )

•Advanced low-power architecture

•High speed: 55 ns, 70 ns

•Wide voltage range: 2.7V to 3.6V

•Typical active current: 1 mA @ f = 1 MHz

•Low standby power

and Write Enable ( WE ) inputs LOW .Data on the eight I/O

pins(I/O₀through I/O₇) is then written into the location

specified on the address pins (A₀through A₁₇).

Reading from the device is accomplished by asserting the

Chip Enable One ( CE ) and Output Enable ( OE ) inputs LOW

•Automatic power-down when deselected

while forcing Write Enable ( WE ) HIGH. Under these

conditions, the contents of the memory location specified by

the address pins will appear on the I/O pins.

Functional Description

The eight input/output pins (I/O₀through I/O₇) are placed in a

The M24L28256SA is a high-performance CMOS pseudo

static RAM (PSRAM) organized as 256K words by 8 bits.

Easy memory expansion is provided by an active LOW Chip

high-impedance state when the device is deselected ( CE

HIGH ), the outputs are disabled ( OE HIGH), or during write

Enable( CE ) and active LOW Output Enable ( OE ).This

device has an automatic power-down feature that reduces

power consumption dramatically when deselected. Writing to

operation ( CE LOW and WE LOW). See the Truth Table

for a complete description of read and write modes.

Logic Block Diagram

Elite Semiconductor Memory Technology Inc.

Publication Date : Jul. 2008

Revision : 1.1

1/12

12 3 4 5 6 7...12

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与M24L28256SA相关器件

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M24L28256SA-70BEG	ESMT	获取价格	2-Mbit (256K x 8) Pseudo Static RAM
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M24L416256DA-55BIG	ESMT	获取价格	4-Mbit (256K x 16) Pseudo Static RAM
M24L416256DA-55TEG	ESMT	获取价格	4-Mbit (256K x 16) Pseudo Static RAM
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