Datasheet > M24L28256DA-55BEG

M24L28256DA-55BEG

更新时间： 2024-01-12 02:58:27

品牌	Logo	应用领域
晶豪 - ESMT		/
页数	文件大小	规格书
10页	225K
描述
2-Mbit (256K x 8) Pseudo Static RAM

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M24L28256DA-55BEG 数据手册

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ESMT

M24L28256DA

PSRAM

2-Mbit (256K x 8)

Pseudo Static RAM

Enable ( WE ) inputs LOW and Chip Enable Two ( CE ₂) input

HIGH. Data on the eight I/O pins (I/O₀through I/O₇) is then

written into the location specified on the address pins (A₀

through A₁₇).

Features

•Advanced low-power architecture

•High speed: 55 ns, 70 ns

•Wide voltage range: 2.7V to 3.3V

•Typical active current: 1 mA @ f = 1 MHz

•Low standby power

Reading from the device is accomplished by asserting the

Chip Enable One ( CE ₁) and Output Enable ( OE ) inputs

LOW while forcing Write Enable ( WE ) HIGH. And Chip

•Automatic power-down when deselected

Enable Two ( CE ) HIGH. Under these conditions, the

contents of the memory location specified by the address pins

will appear on the I/O pins.

Functional Description

The eight input/output pins (I/O₀through I/O₇) are placed in a

The M24L28256DA is a high-performance CMOS pseudo

static RAM (PSRAM) organized as 256K words by 8 bits.

Easy memory expansion is provided by an active LOW Chip

high-impedance state when the device is deselected ( CE ₁

HIGH or CE₂LOW), the outputs are disabled ( OE HIGH), or

Enable( CE ₁) and active HIGH Chip Enable ( CE ₂),and active

during write operation ( CE ₁LOW, CE₂HIGH, and WE

LOW). See the Truth Table for a complete description of read

and write modes.

LOW Output Enable ( OE ).This device has an automatic

power-down feature that reduces power consumption

dramatically when deselected. Writing to the device is

accomplished by asserting Chip Enable One ( CE ₁) and Write

Logic Block Diagram

Elite Semiconductor Memory Technology Inc.

Publication Date : Jul. 2007

Revision : 1.0

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