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M24L216128SA-55BEG PDF预览

M24L216128SA-55BEG

更新时间： 2024-01-29 01:46:12
品牌 Logo 应用领域
晶豪 - ESMT 存储内存集成电路静态存储器
页数 文件大小 规格书
14页 340K
描述
2-Mbit (128K x 16) Pseudo Static RAM

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中文翻译

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M24L216128SA-55BEG 技术参数

生命周期：Contact Manufacturer零件包装代码：TSOP2
包装说明：TSOP2,针数：44
Reach Compliance Code：unknownECCN代码：3A991.B.2.A
HTS代码：8542.32.00.41风险等级：5.52
Is Samacsys：N最长访问时间：55 ns
JESD-30 代码：R-PDSO-G44长度：18.41 mm
内存密度：2097152 bit内存集成电路类型：PSEUDO STATIC RAM
内存宽度：16功能数量：1
端子数量：44字数：131072 words
字数代码：128000工作模式：ASYNCHRONOUS
最高工作温度：85 °C最低工作温度：-25 °C
组织：128KX16封装主体材料：PLASTIC/EPOXY
封装代码：TSOP2封装形状：RECTANGULAR
封装形式：SMALL OUTLINE, THIN PROFILE并行/串行：PARALLEL
认证状态：Not Qualified座面最大高度：1.2 mm
最大供电电压 (Vsup)：3.6 V最小供电电压 (Vsup)：2.7 V
标称供电电压 (Vsup)：3 V表面贴装：YES
技术：CMOS温度等级：OTHER
端子形式：GULL WING端子节距：0.8 mm
端子位置：DUAL宽度：10.16 mm
Base Number Matches：1

M24L216128SA-55BEG 数据手册

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ESMT  
M24L216128SA  
PSRAM  
2-Mbit (128K x 16)  
Pseudo Static RAM  
when both Byte High Enable and Byte Low Enable are  
disabled ( BHE , BLE HIGH), or during a write operation  
Features  
• Wide voltage range: 2.7V–3.6V  
( CE LOW and WE LOW).  
• Access Time: 55 ns, 70 ns  
• Ultra-low active power  
Writing to the device is accomplished by asserting Chip  
— Typical active current: 1mA @ f = 1 MHz  
— Typical active current: 14 mA @ f = fmax (For 55-ns)  
—Typical active current: 8 mA @ f = fmax (For 70-ns)  
• Ultra low standby power  
Enable ( CE LOW) and Write Enable ( WE ) input LOW. If  
Byte Low Enable (BLE ) is LOW, then data from I/O pins (I/O0  
through I/O7), is written into the location specified on the  
• Automatic power-down when deselected  
• CMOS for optimum speed/power  
address pins (A0 through A16). If Byte High Enable (BHE ) is  
LOW, then data from I/O pins (I/O8 through I/O15) is written  
into the location specified on the address pins (A0 through  
A16).  
Functional Description  
Reading from the device is accomplished by asserting Chip  
The M24L216128SA is a high-performance CMOS Pseudo  
Static RAM organized as 128K words by 16 bits that supports  
an asynchronous memory interface. This device features  
advanced circuit design to provide ultra-low active current.  
This is ideal for portable applications such as cellular  
telephones. The device can be put into standby mode when  
Enable ( CE LOW) and Output Enable ( OE ) LOW while  
forcing the Write Enable ( WE ) HIGH. If Byte Low Enable  
(BLE ) is LOW, then data from the memory location specified  
by the address pins will appear on I/O0 to I/O7. If Byte High  
Enable(BHE ) is LOW, then data from memory will appear on  
I/O8 to I/O15. Refer to the truth table for a complete description  
of read and write modes.  
deselected ( CE HIGH or both BHE and BLE are HIGH).  
The input/output pins (I/O0 through I/O15) are placed in a  
high-impedance state when the chip is deselected ( CE  
HIGH), or when the outputs are disabled ( OE HIGH), or  
Logic Block Diagram  
Elite Semiconductor Memory Technology Inc.  
Publication Date : Jul. 2008  
Revision : 1.2  
1/14  
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