Datasheet > 存储 > SRAM> M24L216128DA-55TIG

M24L216128DA-55TIG

更新时间： 2024-02-04 15:49:07

品牌	Logo	应用领域
晶豪 - ESMT		/
页数	文件大小	规格书
14页	345K
描述
2-Mbit (128K x 16) Pseudo Static RAM

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M24L216128DA-55TIG 数据手册

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ESMT

M24L216128DA

PSRAM

2-Mbit (128K x 16)

Pseudo Static RAM

Features

Functional Description

‧Advanced low-power architecture

The M24L216128DA is a high-performance CMOS pseudo

static RAM (PSRAM) organized as 128K words by 16 bits that

supports an asynchronous memory interface. This device

features advanced circuit design to provide ultra-low active

current. This is ideal for portable applications such as cellular

telephones. The device can be put into standby mode,

reducing power consumption dramatically when deselected

• High speed: 55 ns, 70 ns

• Wide voltage range: 2.7V to 3.6V

• Typical active current: 1 mA @ f = 1 MHz

• Low standby power

• Automatic power-down when deselected

( CE1 HIGH, CE2 LOW or both BHE and BLE are HIGH).

The input/output pins(I/O₀through I/O₁₅) are placed in a

high-impedance state when the chip is deselected ( CE1

HIGH, CE2 LOW) or OE is deasserted HIGH), or during a

write operation (Chip Enabled and Write Enable WE LOW).

Reading from the device is accomplished by asserting the

Chip Enables ( CE1 LOW and CE2 HIGH) and Output Enable

(OE) LOW while forcing the Write Enable ( WE ) HIGH. If Byte

Low Enable ( BLE ) is LOW, then data from the memory

location specified by the address pins will appear on I/O₀to

I/O₇. If Byte High Enable ( BHE ) is LOW, then data from

memory will appear on I/O₈to I/O₁₅. Seethe Truth Table for a

complete description of read and write modes.

Logic Block Diagram

Elite Semiconductor Memory Technology Inc.

Publication Date : Jul. 2008

Revision : 1.2

1/14

12 3 4 5 6 7...14

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