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M24L16161ZA-70BEG PDF预览

M24L16161ZA-70BEG

更新时间： 2024-02-19 02:32:26
品牌 Logo 应用领域
晶豪 - ESMT 内存集成电路
页数 文件大小 规格书
21页 407K
描述
Pseudo Static RAM, 1MX16, 70ns, CMOS, PBGA48, 6 X 8 MM, 1 MM HEIGHT, 0.80 MM PITCH, BGA-48

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M24L16161ZA-70BEG 技术参数

生命周期：Contact Manufacturer包装说明：VFBGA,
Reach Compliance Code：unknown风险等级：5.8
最长访问时间：70 nsJESD-30 代码：R-PBGA-B48
长度：8 mm内存密度：16777216 bit
内存集成电路类型：PSEUDO STATIC RAM内存宽度：16
功能数量：1端子数量：48
字数：1048576 words字数代码：1000000
工作模式：ASYNCHRONOUS组织：1MX16
封装主体材料：PLASTIC/EPOXY封装代码：VFBGA
封装形状：RECTANGULAR封装形式：GRID ARRAY, VERY THIN PROFILE, FINE PITCH
并行/串行：PARALLEL座面最大高度：1 mm
最大供电电压 (Vsup)：3.3 V最小供电电压 (Vsup)：2.7 V
标称供电电压 (Vsup)：3 V表面贴装：YES
技术：CMOS端子形式：BALL
端子节距：0.75 mm端子位置：BOTTOM
宽度：6 mmBase Number Matches：1

M24L16161ZA-70BEG 数据手册

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ESMT  
PSRAM  
M24L16161ZA  
16-Mbit (1M x 16)  
Async / Page Pseudo Static RAM  
Features  
• Voltage range: 2.7V – 3.3 V  
• Access Time: 70 ns  
• Ultra-low active power  
— Maximum active current: 20 mA (for random Read/ Write)  
— Maximum active current: 20 mA (for page Read)  
• Ultra low standby power  
• 16-word Page Mode  
• Low-power features:  
— Temperature-compensated refresh (TCR)  
— On-chip temperature sensor  
— Partial-array refresh (PAR)  
— Deep power-down (DPD) mode  
• CMOS for optimum speed/power  
• Operating Temperature (TC): –25°C to +85°C (Extended)  
Ordering Information  
Speed  
(ns)  
Operating  
Comments  
Temperature  
Product ID  
Package  
M24L16161ZA-70BEG  
70  
48-ball BGA  
Extended  
Pb-free  
Functional Description  
The device is a high-performance CMOS Pseudo Static RAM  
organized as 1M words by 16 bits that supports an  
asynchronous memory interface. This device features  
advanced circuit design to provide ultra-low active current.  
This is ideal for portable applications such as cellular  
telephones. A refresh configuration register (RCR) is used to  
control how refresh is performed on the DRAM array. This  
register is automatically loaded with default settings during  
power-up and can be updated anytime during normal  
operation.  
uses an on-chip sensor to adjust the refresh rate to match the  
device temperature. The refresh rate decreases at lower  
temperatures to minimize current consumption during standby.  
Setting sleep enable ( ZZ ) to LOW enables one of two  
low-power modes: partial-array refresh (PAR) or deep  
power-down (DPD). PAR limits refresh to only that part of the  
DRAM array that contains essential data. DPD halts refresh  
operation altogether and is used when no vital information is  
stored in the device. The system-configurable refresh  
mechanisms are accessed through the RCR.  
There are three system-accessible mechanisms to minimize  
refresh current. Temperature-compensated refresh (TCR)  
Elite Semiconductor Memory Technology Inc.  
Publication Date : Dec. 2010  
Revision: 1.0  
1/21  
1234567...21

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