Datasheet > M14D5121632A-2.5BG

M14D5121632A-2.5BG

更新时间： 2024-09-24 05:44:31

品牌	Logo	应用领域
晶豪 - ESMT		动态存储器双倍数据速率
页数	文件大小	规格书
59页	975K
描述
8M x 16 Bit x 4 Banks DDR II SDRAM

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数据手册

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ESMT

M14D5121632A

8M x 16 Bit x 4 Banks

DDR II SDRAM

Features

JEDEC Standard

V_DD= 1.8V ± 0.1V, V_DDQ= 1.8V ± 0.1V

Internal pipelined double-data-rate architecture; two data access per clock cycle

Bi-directional differential data strobe (DQS, /DQS); /DQS can be disabled for single-ended data strobe operation.

On-chip DLL

Differential clock inputs (CLK and CLK )

DLL aligns DQ and DQS transition with CLK transition

Quad bank operation

CAS Latency : 3, 4, 5, 6

Additive Latency: 0, 1, 2, 3, 4

Burst Type : Sequential and Interleave

Burst Length : 4, 8

All inputs except data & DM are sampled at the rising edge of the system clock(CLK)

Data I/O transitions on both edges of data strobe (DQS)

DQS is edge-aligned with data for READ; center-aligned with data for WRITE

Data mask (DM) for write masking only

Off-Chip-Driver (OCD) impedance adjustment

On-Die-Termination for better signal quality

Special function support

50/ 75/ 150 ohm ODT

High Temperature Self refresh rate enable

Auto & Self refresh

Refresh cycle :

8192 cycles/64ms (7.8μs refresh interval) at 0 ℃ ≦ T_C≦ +85 ℃

8192 cycles/32ms (3.9μs refresh interval) at +85 ℃ ＜ T_C≦ +95 ℃

SSTL_18 interface

84-ball BGA package

Ordering Information:

Data rate

PRODUCT NO.

MAX FREQ

VDD

PACKAGE COMMENTS

(CL-tRCD-tRP)

DDR2-800 (5-5-5)

DDR2-800 (6-6-6)

DDR2-667 (5-5-5)

M14D5121632A -2.5BG

M14D5121632A -3BG

400MHz

333MHz

1.8V

BGA

Pb-free

Elite Semiconductor Memory Technology Inc.

Publication Date : Feb. 2009

Revision : 1.1 1/59

12 3 4 5 6 7...59

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