Datasheet > M13S64164A-4BVG2Y

M13S64164A-4BVG2Y

更新时间： 2024-02-11 01:19:03

品牌	Logo	应用领域
晶豪 - ESMT		动态存储器双倍数据速率
页数	文件大小	规格书
49页	1219K
描述
DDR DRAM, 4MX16, 0.7ns, CMOS, PBGA60, 8 X 13 MM, 1.20 MM HEIGHT, 0.80 MM PITCH, LEAD FREE, BGA-60

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M13S64164A-4BVG2Y 数据手册

ESMT

DDR SDRAM

Features

M13S64164A (2Y)

Automotive Grade

1M x 16 Bit x 4 Banks

Double Data Rate SDRAM

Double-data-rate architecture, two data transfers per clock cycle

Bi-directional data strobe (DQS)

Differential clock inputs (CLK and CLK )

DLL aligns DQ and DQS transition with CLK transition

Four bank operation

CAS Latency : 2, 2.5, 3

Burst Type : Sequential and Interleave

Burst Length : 2, 4, 8

All inputs except data & DM are sampled at the rising edge of the system clock (CLK)

Data I/O transitions on both edges of data strobe (DQS)

DQS is edge-aligned with data for READs; center-aligned with data for WRITEs

Data mask (DM) for write masking only

V_DD= 2.5V ± 0.2V, V_DDQ= 2.5V ± 0.2V

15.6us refresh interval for V grade; 3.9us refresh interval for VA grade

Auto & Self refresh (self refresh is not supported for VA grade)

2.5V I/O (SSTL_2 compatible)

Elite Semiconductor Memory Technology Inc.

Publication Date : Oct. 2012

Revision : 1.0 1/49

12 3 4 5 6 7...49

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型号	品牌	描述	获取价格	数据表
M13S64164A-4TG2Y	ESMT	DDR DRAM, 4MX16, 0.7ns, CMOS, PDSO66, 0.400 X 0.875 INCH, 0.65 MM PITCH, LEAD FREE, TSOP2-	获取价格
M13S64164A-4TVAG2Y	ESMT	DDR DRAM, 4MX16, 0.7ns, CMOS, PDSO66, 0.400 X 0.875 INCH, 0.65 MM PITCH, LEAD FREE, TSOP2-	获取价格
M13S64164A-4TVG2Y	ESMT	DDR DRAM, 4MX16, 0.7ns, CMOS, PDSO66, 0.400 X 0.875 INCH, 0.65 MM PITCH, LEAD FREE, TSOP2-	获取价格
M13S64164A-5BG	ESMT	1M x 16 Bit x 4 Banks Double Data Rate SDRAM	获取价格
M13S64164A-5BG2Y	ESMT	DDR DRAM, 4MX16, 0.7ns, CMOS, PBGA60, 8 X 13 MM, 1.20 MM HEIGHT, 0.80 MM PITCH, LEAD FREE,	获取价格
M13S64164A-5BIG	ESMT	1M x 16 Bit x 4 Banks Double Data Rate SDRAM	获取价格