M13S5121632A-5TG

更新时间： 2024-01-29 18:08:23

品牌	Logo	应用领域
晶豪 - ESMT		动态存储器双倍数据速率
页数	文件大小	规格书
47页	966K
描述
8M x 16 Bit x 4 Banks Double Data Rate SDRAM

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中文翻译

获取价格

数据手册

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M13S5121632A-5TG 数据手册

ESMT

DDR SDRAM

M13S5121632A

8M x 16 Bit x 4 Banks

Double Data Rate SDRAM

Features

JEDEC Standard

Internal pipelined double-data-rate architecture, two data access per clock cycle

Bi-directional data strobe (DQS)

On-chip DLL

Differential clock inputs (CLK and CLK )

DLL aligns DQ and DQS transition with CLK transition

Quad bank operation

CAS Latency : 2; 2.5; 3

Burst Type : Sequential and Interleave

Burst Length : 2, 4, 8

All inputs except data & DM are sampled at the rising edge of the system clock(CLK)

Data I/O transitions on both edges of data strobe (DQS)

DQS is edge-aligned with data for reads; center-aligned with data for WRITE

Data mask (DM) for write masking only

V_DD, V_DDQ= 2.5V ~ 2.7V

Auto & Self refresh

7.8us refresh interval (64ms refresh period, 8K cycle)

SSTL-2 I/O interface

66pin TSOPII package

Ordering information:

PRODUCT ID

MAX FREQ

VDD

PACKAGE

COMMENTS

M13S5121632A -5TG

200MHz

2.5V

TSOPII

Pb-free

Elite Semiconductor Memory Technology Inc.

Publication Date : Oct. 2008

Revision : 1.0 1/47

12 3 4 5 6 7...47

中文翻译

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