Datasheet > M13S32321A-5BG2G

M13S32321A-5BG2G

更新时间： 2023-02-26 14:43:31

品牌	Logo	应用领域
晶豪 - ESMT		动态存储器双倍数据速率
页数	文件大小	规格书
48页	1146K
描述
DDR DRAM, 1MX32, 0.7ns, CMOS, PBGA144, FBGA-144

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中文翻译

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数据手册

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M13S32321A-5BG2G 数据手册

ESMT

DDR SDRAM

M13S32321A (2G)

512K x 32 Bit x 2 Banks

Double Data Rate SDRAM

Features

Double-data-rate architecture, two data transfers per clock cycle

Bi-directional data strobe (DQS)

Differential clock inputs (CLK and CLK )

DLL aligns DQ and DQS transition with CLK transition

Two bank operation

CAS Latency : 2, 2.5, 3

Burst Type : Sequential and Interleave

Burst Length : 2, 4, 8

All inputs except data & DM are sampled at the rising edge of the system clock(CLK)

Data I/O transitions on both edges of data strobe (DQS)

DQS is edge-aligned with data for READs; center-aligned with data for WRITEs

Data mask (DM) for write masking only

V_DD= 2.3V ~ 2.7V, V_DDQ= 2.3V ~ 2.7V

Auto & Self refresh

15.6us refresh interval

2.5V I/O (SSTL_2 compatible)

Ordering Information

Product ID

Max Freq.

V_DD

2.5V

Package

Comments

M13S32321A -5BG2G

M13S32321A -6BG2G

M13S32321A -7.5BG2G

200MHz (DDR400)

166MHz (DDR333)

133MHz (DDR266)

144 ball FBGA

Pb-free

Elite Semiconductor Memory Technology Inc.

Publication Date : Aug. 2012

Revision : 1.0

1/48

12 3 4 5 6 7...48

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与M13S32321A-5BG2G相关器件

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