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M13S128324A-5BIG2M PDF预览

M13S128324A-5BIG2M

更新时间: 2024-09-24 14:43:15
品牌 Logo 应用领域
晶豪 - ESMT 动态存储器双倍数据速率内存集成电路
页数 文件大小 规格书
48页 1151K
描述
DDR DRAM, 4MX32, 0.7ns, CMOS, PBGA144, 12 X 12 MM, 1.40 MM HEIGHT, 0.80 MM PITCH, LEAD FREE, MO-205, FBGA-144

M13S128324A-5BIG2M 技术参数

生命周期:Contact Manufacturer包装说明:LFBGA,
Reach Compliance Code:unknown风险等级:5.67
访问模式:FOUR BANK PAGE BURST最长访问时间:0.7 ns
其他特性:AUTO/SELF REFRESHJESD-30 代码:S-PBGA-B144
长度:12 mm内存密度:134217728 bit
内存集成电路类型:DDR DRAM内存宽度:32
功能数量:1端口数量:1
端子数量:144字数:4194304 words
字数代码:4000000工作模式:SYNCHRONOUS
最高工作温度:85 °C最低工作温度:-40 °C
组织:4MX32封装主体材料:PLASTIC/EPOXY
封装代码:LFBGA封装形状:SQUARE
封装形式:GRID ARRAY, LOW PROFILE, FINE PITCH座面最大高度:1.4 mm
自我刷新:YES最大供电电压 (Vsup):2.625 V
最小供电电压 (Vsup):2.357 V标称供电电压 (Vsup):2.5 V
表面贴装:YES技术:CMOS
温度等级:INDUSTRIAL端子形式:BALL
端子节距:0.8 mm端子位置:BOTTOM
宽度:12 mmBase Number Matches:1

M13S128324A-5BIG2M 数据手册

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ESMT  
M13S128324A (2M)  
Operation Temperature Condition -40°C~85°C  
DDR SDRAM  
1M x 32 Bit x 4 Banks  
Double Data Rate SDRAM  
Features  
z
Double-data-rate architecture, two data transfers per clock cycle  
z
Bi-directional data strobe (DQS)  
z
z
Differential clock inputs (CLK and CLK )  
DLL aligns DQ and DQS transition with CLK transition  
Quad bank operation  
z
z
z
z
z
z
z
z
z
z
z
z
z
CAS Latency : 2, 2.5, 3  
Burst Type : Sequential and Interleave  
Burst Length : 2, 4, 8  
All inputs except data & DM are sampled at the rising edge of the system clock(CLK)  
Data I/O transitions on both edges of data strobe (DQS)  
DQS is edge-aligned with data for READs; center-aligned with data for WRITEs  
Data mask (DM) for write masking only  
VDD = 2.375V ~ 2.625V, VDDQ = 2.375V ~ 2.625V  
VDD = 2.5V ~ 2.7V, VDDQ = 2.5V ~ 2.7V (for speed -3.6)  
Auto & Self refresh  
32ms refresh period (4K cycle)  
2.5V I/O (SSTL_2 compatible)  
Ordering Information  
Product ID  
Max Freq.  
VDD  
2.6V  
2.5V  
2.5V  
2.5V  
Package  
Comments  
M13S128324A -3.6BIG2M  
M13S128324A -4BIG2M  
M13S128324A -5BIG2M  
M13S128324A -6BIG2M  
275MHz (DDR550)  
250MHz (DDR500)  
200MHz (DDR400)  
166MHz (DDR333)  
144 ball FBGA  
Pb-free  
Elite Semiconductor Memory Technology Inc.  
Publication Date : Dec. 2010  
Revision : 1.0  
1/48  

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