ESMT
M12S16161A
Operation Temperature Condition -40°C~85°C
SDRAM
512K x 16Bit x 2Banks
Synchronous DRAM
FEATURES
GENERAL DESCRIPTION
The M12S16161A is 16,777,216 bits synchronous high
data rate Dynamic RAM organized as 2 x 524,288 words by
16 bits, fabricated with high performance CMOS technology.
Synchronous design allows precise cycle control with the
use of system clock I/O transactions are possible on every
clock cycle. Range of operating frequencies, programmable
burst length and programmable latencies allow the same
device to be useful for a variety of high bandwidth, high
performance memory system applications.
z
z
z
z
JEDEC standard 2.5V power supply
LVTTL compatible with multiplexed address
Dual banks operation
MRS cycle with address key programs
-
-
-
CAS Latency (2 & 3 )
Burst Length (1, 2, 4, 8 & full page)
Burst Type (Sequential & Interleave)
z
All inputs are sampled at the positive going edge of the
system clock
z
z
z
z
Burst Read Single-bit Write operation
DQM for masking
Auto & self refresh
ORDERING INFORMATION
32ms refresh period (2K cycle)
Part NO.
MAX Freq. PACKAGE COMMENTS
M12S16161A-6TIG
M12S16161A-7TIG
M12S16161A-6BIG
M12S16161A-7BIG
TSOP(II)
TSOP(II)
VFBGA
VFBGA
Pb-free
Pb-free
Pb-free
Pb-free
166MHz
143MHz
166MHz
143MHz
PIN CONFIGURATION (TOP VIEW)
1
2
3
4
5
6
7
DQ0
VDD
A
B
C
D
E
F
VSS
DQ15
VDD
DQ0
DQ1
VSSQ
DQ2
DQ3
VDDQ
DQ4
DQ5
VSSQ
DQ6
DQ7
VDDQ
LDQM
WE
1
VSS
50
49
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
VDDQ
VSSQ
DQ1
DQ2
DQ14
DQ13
VSSQ
VDDQ
2
DQ15
DQ14
VSSQ
DQ13
DQ12
VDDQ
DQ11
DQ10
VSSQ
DQ9
DQ8
VDDQ
N.C/RFU
UDQM
CLK
CKE
N.C
3
4
DQ4
DQ3
DQ5
5
DQ12
DQ10
DQ9
DQ11
VSSQ
6
VDDQ
7
8
VSSQ
NC
VDDQ
NC
DQ6
DQ7
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
G
H
J
DQ8
NC
NC
NC
NC
NC
UDQM
LDQM
WE
CLK
NC
A9
RAS
NC
NC
CAS
CS
K
L
CAS
RAS
CS
CKE
BA
A9
NC
NC
A0
BA
A8
M
N
P
R
A10/AP
A0
A8
A10
A7
A7
A1
A6
A1
A5
A4
A2
A3
A6
A2
A5
A3
A4
50PIN TSOP(II)
(400mil x 825mil)
60 Ball VFBGA
(6.4x10.1mm)
(0.65mm ball pitch)
VDD
VSS
VDD
VSS
(0.8 mm PIN PITCH)
Elite Semiconductor Memory Technology Inc.
Publication Date : Sep. 2007
Revision : 1.0 1/30