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M12S16161A-7TG2Q PDF预览

M12S16161A-7TG2Q

更新时间: 2024-01-02 14:21:08
品牌 Logo 应用领域
晶豪 - ESMT 动态存储器光电二极管内存集成电路
页数 文件大小 规格书
28页 389K
描述
Synchronous DRAM, 1MX16, 6ns, CMOS, PDSO50, 0.400 X 0.825 INCH, 0.80 MM PITCH, LEAD FREE, TSOP2-50

M12S16161A-7TG2Q 技术参数

生命周期:Contact Manufacturer包装说明:TSOP2,
Reach Compliance Code:unknown风险等级:5.72
Is Samacsys:N访问模式:DUAL BANK PAGE BURST
最长访问时间:6 ns其他特性:AUTO/SELF REFRESH
JESD-30 代码:R-PDSO-G50长度:20.95 mm
内存密度:16777216 bit内存集成电路类型:SYNCHRONOUS DRAM
内存宽度:16功能数量:1
端口数量:1端子数量:50
字数:1048576 words字数代码:1000000
工作模式:SYNCHRONOUS最高工作温度:70 °C
最低工作温度:组织:1MX16
封装主体材料:PLASTIC/EPOXY封装代码:TSOP2
封装形状:RECTANGULAR封装形式:SMALL OUTLINE, THIN PROFILE
座面最大高度:1.2 mm自我刷新:YES
最大供电电压 (Vsup):2.7 V最小供电电压 (Vsup):2.3 V
标称供电电压 (Vsup):2.5 V表面贴装:YES
技术:CMOS温度等级:COMMERCIAL
端子形式:GULL WING端子节距:0.8 mm
端子位置:DUAL宽度:10.16 mm
Base Number Matches:1

M12S16161A-7TG2Q 数据手册

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ESMT  
M12S16161A (2Q)  
SDRAM  
512K x 16Bit x 2Banks  
Synchronous DRAM  
FEATURES  
GENERAL DESCRIPTION  
The M12S16161A is 16,777,216 bits synchronous high data  
rate Dynamic RAM organized as 2 x 524,288 words by 16 bits,  
fabricated with high performance CMOS technology.  
Synchronous design allows precise cycle control with the use  
of system clock I/O transactions are possible on every clock  
cycle. Range of operating frequencies, programmable burst  
length and programmable latencies allow the same device to  
be useful for a variety of high bandwidth, high performance  
memory system applications.  
JEDEC standard 2.5V power supply  
LVTTL compatible with multiplexed address  
Dual banks operation  
MRS cycle with address key programs  
-
-
-
CAS Latency (2 & 3 )  
Burst Length (1, 2, 4, 8 & full page)  
Burst Type (Sequential & Interleave)  
All inputs are sampled at the positive going edge of the  
system clock  
Burst Read Single-bit Write operation  
DQM for masking  
Auto & self refresh  
ORDERING INFORMATION  
32ms refresh period (2K cycle)  
Product ID  
Max Freq.  
Package  
Comments  
M12S16161A-5TG2Q  
M12S16161A-7TG2Q  
TSOP(II)  
TSOP(II)  
Pb-free  
Pb-free  
200MHz  
143MHz  
PIN CONFIGURATION (TOP VIEW)  
(TSOPII 50L, 400milX825mil Body, 0.8mm Pin Pitch)  
VDD  
DQ0  
DQ1  
VSSQ  
DQ2  
DQ3  
VDDQ  
DQ4  
DQ5  
VSSQ  
DQ6  
DQ7  
VDDQ  
LDQM  
WE  
1
VSS  
50  
49  
48  
47  
46  
45  
44  
43  
42  
41  
40  
39  
38  
37  
36  
35  
34  
33  
32  
31  
30  
29  
28  
27  
26  
2
DQ15  
DQ14  
VSSQ  
DQ13  
DQ12  
VDDQ  
DQ11  
DQ10  
VSSQ  
DQ9  
DQ8  
VDDQ  
N.C/RFU  
UDQM  
CLK  
CKE  
N.C  
3
4
5
6
7
8
9
10  
11  
12  
13  
14  
15  
16  
17  
18  
19  
20  
21  
22  
23  
24  
25  
CAS  
RAS  
CS  
BA  
A9  
A10/AP  
A0  
A8  
A7  
A1  
A6  
A2  
A5  
A3  
A4  
VDD  
VSS  
Elite Semiconductor Memory Technology Inc.  
Publication Date : Mar. 2012  
Revision : 1.0 1/28  

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