Datasheet > M12S128324A-7TG

M12S128324A-7TG

更新时间： 2024-01-12 19:34:24

品牌	Logo	应用领域
晶豪 - ESMT		动态存储器
页数	文件大小	规格书
46页	742K
描述
1M x 32 Bit x 4 Banks Synchronous DRAM

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技术参数
数据手册

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M12S128324A-7TG 技术参数

生命周期：	Contact Manufacturer	包装说明：	,
Reach Compliance Code：	unknown	风险等级：	5.75
Base Number Matches：	1

M12S128324A-7TG 数据手册

ESMT

SDRAM

M12S128324A

1M x 32 Bit x 4 Banks

Synchronous DRAM

FEATURES

JEDEC standard 2.5V power supply

LVTTL compatible with multiplexed address

Four banks operation

MRS cycle with address key programs

- CAS Latency (1, 2 & 3 )

- Burst Length ( 1, 2, 4, 8 & full page )

- Burst Type ( Sequential & Interleave )

All inputs are sampled at the positive going edge of the

system clock

DQM for masking

Auto & self refresh

64ms refresh period (4K cycle)

ORDERING INFORMATION

MAX

Product No.

PACKAGE COMMENTS

FREQ.

M12S128324A-6TG 166MHz 86 TSOPII

M12S128324A-6BG 166MHz 90 FBGA

M12S128324A-7TG 143MHz 86 TSOPII

Pb-free

M12S128324A-7BG 143MHz

90 FBGA

GENERAL DESCRIPTION

The M12S128324A is 134,217,728 bits synchronous high data rate Dynamic RAM organized as 4 x 1,048,576 words by 32 bits.

Synchronous design allows precise cycle control with the use of system clock I/O transactions are possible on every clock cycle.

Range of operating frequencies, programmable burst length and programmable latencies allow the same device to be useful for a

variety of high bandwidth, high performance memory system applications.

Elite Semiconductor Memory Technology Inc.

Publication Date: Mar. 2009

Revision: 1.4 1/46

12 3 4 5 6 7...46

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