ESMT
M12L64322A (2U)
Operation Temperature Condition -40°C~85°C
SDRAM
512K x 32 Bit x 4 Banks
Synchronous DRAM
FEATURES
ORDERING INFORMATION
y
y
y
y
JEDEC standard 3.3V power supply
LVTTL compatible with multiplexed address
Four banks operation
MRS cycle with address key programs
- CAS Latency ( 2 & 3 )
- Burst Length ( 1, 2, 4, 8 & full page )
- Burst Type ( Sequential & Interleave )
All inputs are sampled at the positive going edge of the
system clock
Product ID
Max Freq. Package
200MHz 86 TSOPII
166MHz 86 TSOPII
143MHz 86 TSOPII
Comments
Pb-free
Pb-free
Pb-free
Pb-free
Pb-free
Pb-free
M12L64322A-5TIG2U
M12L64322A-6TIG2U
M12L64322A-7TIG2U
y
M12L64322A-5BIG2U 200MHz
M12L64322A-6BIG2U 166MHz
M12L64322A-7BIG2U 143MHz
90 BGA
90 BGA
90 BGA
y
y
y
DQM for masking
Auto & self refresh
15.6μs refresh interval
GENERAL DESCRIPTION
The M12L64322A is 67,108,864 bits synchronous high data rate Dynamic RAM organized as 4 x 524,288 words by 32 bits.
Synchronous design allows precise cycle control with the use of system clock I/O transactions are possible on every clock cycle.
Range of operating frequencies, programmable burst length and programmable latencies allow the same device to be useful for a
variety of high bandwidth, high performance memory system applications.
PIN CONFIGURATION (TOP VIEW)
(TSOPII 86L, 400milX875mil Body, 0.5mm Pin Pitch)
V
DD
1
2
3
4
5
6
7
8
86
85
84
83
82
81
80
79
78
77
76
75
74
73
72
71
70
69
68
67
V
S S
DQ0
DQ15
V
DDQ
DQ1
DQ2
V
S S Q
DQ14
DQ13
V
SS Q
DQ3
DQ4
V
DD Q
DQ12
DQ11
9
V
DDQ
DQ5
DQ6
V
S S Q
10
11
12
13
14
15
16
17
18
19
20
DQ10
DQ9
V
SS Q
DQ7
NC
VDD Q
DQ8
NC
V
DD
V
S S
DQM0
WE
DQM1
NC
CAS
RAS
CS
NC
CLK
CKE
A9
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
66
65
64
63
62
61
60
59
58
57
56
55
54
53
52
51
50
49
48
47
46
45
44
NC
A8
BA0
BA1
A10/AP
A0
A7
A6
A5
A4
A1
A3
A2
DQM3
DQM2
V
S S
V
DD
NC
NC
DQ16
DQ31
V
DDQ
V
SS Q
DQ17
DQ18
DQ30
DQ29
V
SS Q
V
DDQ
DQ28
DQ27
DQ19
DQ20
V
DDQ
V
SS Q
DQ26
DQ25
DQ21
DQ22
V
SS Q
V
DDQ
DQ23
DQ24
V
SS
V
DD
Elite Semiconductor Memory Technology Inc.
Publication Date: Oct. 2011
Revision: 1.0 1/46