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M12L64322A-6T PDF预览

M12L64322A-6T

更新时间: 2024-09-24 05:44:31
品牌 Logo 应用领域
晶豪 - ESMT 存储内存集成电路光电二极管动态存储器时钟
页数 文件大小 规格书
44页 812K
描述
512K x 32 Bit x 4 Banks Synchronous DRAM

M12L64322A-6T 技术参数

生命周期:Obsolete包装说明:TSSOP, TSSOP86,.46,20
Reach Compliance Code:unknown风险等级:5.8
Is Samacsys:N最长访问时间:5.5 ns
最大时钟频率 (fCLK):166 MHzI/O 类型:COMMON
交错的突发长度:1,2,4,8JESD-30 代码:R-PDSO-G86
内存密度:67108864 bit内存集成电路类型:SYNCHRONOUS DRAM
内存宽度:32端子数量:86
字数:2097152 words字数代码:2000000
最高工作温度:70 °C最低工作温度:
组织:2MX32输出特性:3-STATE
封装主体材料:PLASTIC/EPOXY封装代码:TSSOP
封装等效代码:TSSOP86,.46,20封装形状:RECTANGULAR
封装形式:SMALL OUTLINE, THIN PROFILE, SHRINK PITCH电源:3.3 V
认证状态:Not Qualified刷新周期:4096
连续突发长度:1,2,4,8,FP最大待机电流:0.002 A
子类别:DRAMs最大压摆率:0.31 mA
标称供电电压 (Vsup):3.3 V表面贴装:YES
技术:CMOS温度等级:COMMERCIAL
端子形式:GULL WING端子节距:0.5 mm
端子位置:DUALBase Number Matches:1

M12L64322A-6T 数据手册

 浏览型号M12L64322A-6T的Datasheet PDF文件第2页浏览型号M12L64322A-6T的Datasheet PDF文件第3页浏览型号M12L64322A-6T的Datasheet PDF文件第4页浏览型号M12L64322A-6T的Datasheet PDF文件第5页浏览型号M12L64322A-6T的Datasheet PDF文件第6页浏览型号M12L64322A-6T的Datasheet PDF文件第7页 
ESMT  
SDRAM  
M12L64322A  
512K x 32 Bit x 4 Banks  
Synchronous DRAM  
FEATURES  
ORDERING INFORMATION  
JEDEC standard 3.3V power supply  
LVTTL compatible with multiplexed address  
Four banks operation  
86 Pin TSOP (TypeII)  
(400mil x 875mil)  
MRS cycle with address key programs  
- CAS Latency ( 2 & 3 )  
- Burst Length ( 1, 2, 4, 8 & full page )  
- Burst Type ( Sequential & Interleave )  
All inputs are sampled at the positive going edge of the  
system clock  
Product No.  
M12L64322A-6T  
M12L64322A-7T  
MAX FREQ.  
166MHz  
PACKAGE  
TSOPII  
143MHz  
DQM for masking  
Auto & self refresh  
15.6μs refresh interval  
GENERAL DESCRIPTION  
The M12L64322A is 67,108,864 bits synchronous high data rate Dynamic RAM organized as 4 x 524,288 words by 32 bits.  
Synchronous design allows precise cycle control wi0th the use of system clock I/O transactions are possible on every clock cycle.  
Range of operating frequencies, programmable burst length and programmable latencies allow the same device to be useful for a  
variety of high bandwidth, high performance memory system applications.  
PIN ARRANGEMENT  
Top View  
VDD  
DQ0  
VDDQ  
DQ1  
DQ2  
VSS Q  
DQ3  
DQ4  
VDDQ  
DQ5  
DQ6  
VS SQ 12  
DQ7  
NC  
VDD 15  
DQM0 16  
WE 17  
CAS  
RAS  
CS  
NC  
BA0  
BA1  
A10/AP  
A0  
A1  
A2  
DQM2  
VDD  
VS S  
1
2
3
4
5
6
7
8
9
86  
85  
84  
83  
82  
81  
80  
79  
78  
77  
76  
75  
74  
73  
72  
71  
70  
69  
68  
67  
DQ15  
VSSQ  
DQ14  
DQ13  
VDDQ  
DQ12  
DQ11  
VSSQ  
DQ10  
DQ9  
VDDQ  
DQ8  
N C  
10  
11  
13  
14  
VSS  
DQM1  
N C  
18  
19  
20  
N C  
CLK  
CKE  
A9  
A8  
A7  
A6  
A5  
A4  
A3  
21  
22  
23  
24  
25  
26  
27  
28  
29  
30  
31  
32  
66  
65  
64  
63  
62  
61  
60  
59  
58  
57  
56  
55  
54  
53  
52  
51  
50  
49  
48  
47  
46  
45  
44  
DQM3  
VS S  
N C  
NC  
DQ16  
VSS Q  
DQ31  
VDDQ  
DQ30  
DQ29  
VSSQ  
DQ28  
DQ27  
VDDQ  
DQ26  
DQ25  
VSSQ  
DQ24  
VS S  
DQ17 33  
DQ18 34  
VDDQ 35  
DQ19 36  
DQ20  
VSS Q  
DQ21  
DQ22  
VDDQ  
37  
38  
39  
40  
41  
DQ23 42  
VDD  
43  
86Pin TSOP(II)  
(400mil x 875mil)  
(0.5mm Pin pitch)  
Elite Semiconductor Memory Technology Inc.  
Publication Date: May. 2004  
Revision: 1.7 1/44  

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