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M12L2561616A PDF预览

M12L2561616A

更新时间: 2024-01-05 15:26:09
品牌 Logo 应用领域
晶豪 - ESMT 动态存储器
页数 文件大小 规格书
44页 890K
描述
4M x 16 Bit x 4 Banks Synchronous DRAM

M12L2561616A 数据手册

 浏览型号M12L2561616A的Datasheet PDF文件第2页浏览型号M12L2561616A的Datasheet PDF文件第3页浏览型号M12L2561616A的Datasheet PDF文件第4页浏览型号M12L2561616A的Datasheet PDF文件第5页浏览型号M12L2561616A的Datasheet PDF文件第6页浏览型号M12L2561616A的Datasheet PDF文件第7页 
ESMT  
M12L2561616A  
SDRAM  
4M x 16 Bit x 4 Banks  
Synchronous DRAM  
FEATURES  
ORDERING INFORMATION  
y
y
y
y
JEDEC standard 3.3V power supply  
LVTTL compatible with multiplexed address  
Four banks operation  
MRS cycle with address key programs  
- CAS Latency ( 2 & 3 )  
- Burst Length ( 1, 2, 4, 8 & full page )  
- Burst Type ( Sequential & Interleave )  
All inputs are sampled at the positive going edge of the  
system clock  
PRODUCT NO.  
M12L2561616A-6TG  
M12L2561616A-6BG  
M12L2561616A-7TG  
M12L2561616A-7BG  
MAX FREQ. PACKAGE COMMENTS  
166MHz  
166MHz  
143MHz  
143MHz  
TSOP II  
BGA  
Pb-free  
Pb-free  
Pb-free  
Pb-free  
TSOP II  
BGA  
y
y
y
y
y
Burst Read single write operation  
DQM for masking  
Auto & self refresh  
64ms refresh period (8K cycle)  
GENERAL DESCRIPTION  
The M12L2561616A is 268,435,456 bits synchronous high data rate Dynamic RAM organized as 4 x 4,194,304 words by 16 bits.  
Synchronous design allows precise cycle control with the use of system clock I/O transactions are possible on every clock cycle.  
Range of operating frequencies, programmable burst length and programmable latencies allow the same device to be useful for a  
variety of high bandwidth, high performance memory system applications.  
Pin Arrangement  
1
2
3
4
5
6
7
8
9
54  
53  
52  
51  
50  
49  
48  
47  
46  
45  
44  
43  
42  
41  
40  
39  
38  
37  
36  
35  
34  
33  
32  
31  
30  
29  
28  
V
SS  
1
V
DD  
DQ15  
2
DQ0  
VSSQ  
VDDQ  
DQ0  
VDD  
A
B
C
D
E
F
VSS  
DQ15  
V
SSQ  
3
V
DDQ  
DQ1  
DQ2  
DQ14  
DQ13  
4
VDDQ  
VSSQ  
VSSQ  
VDDQ  
DQ2  
DQ4  
DQ1  
DQ3  
DQ14  
DQ12  
DQ13  
DQ11  
5
V
DDQ  
6
V
SSQ  
DQ3  
DQ4  
DQ12  
DQ11  
7
8
V
SSQ  
9
V
DDQ  
DQ5  
DQ6  
VSSQ  
VDD  
DQ6  
DQ10  
DQ8  
DQ9  
NC  
VDDQ  
VSS  
DQ5  
DQ7  
DQ10  
DQ9  
10  
11  
12  
13  
14  
15  
16  
17  
18  
19  
20  
21  
22  
23  
24  
25  
26  
27  
LDQM  
V
DDQ  
V
SSQ  
DQ8  
DQ7  
V
SS  
V
DD  
UDQM  
A12  
CLK  
A11  
CKE  
A9  
CAS  
BA0  
RAS  
BA1  
WE  
CS  
NC  
LDQM  
WE  
UDQM  
CLK  
CKE  
G
H
J
CAS  
RAS  
CS  
A8  
A0  
A3  
A10  
A7  
A5  
A6  
A4  
A1  
A2  
A
A
A
A
A
A
A
A
V
12  
11  
9
BA0  
BA1  
VSS  
VDD  
8
A
10/AP  
7
A
A
A
A
0
1
2
3
6
5
4
SS  
V
DD  
Elite Semiconductor Memory Technology Inc.  
Publication Date: Aug. 2007  
Revision: 1.2 1/44  

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