Datasheet > M12L16161A-5TIG2Q

M12L16161A-5TIG2Q

更新时间： 2023-02-26 14:51:08

品牌	Logo	应用领域
晶豪 - ESMT		动态存储器光电二极管
页数	文件大小	规格书
28页	706K
描述
Synchronous DRAM, 1MX16, 4.5ns, CMOS, PDSO50, 0.400 X 0.875 INCH, 0.80 MM PITCH, LEAD FREE, TSOP2-50

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ESMT

M12L16161A (2Q)

Operation Temperature Condition -40°C~85°C

SDRAM

512K x 16Bit x 2Banks

Synchronous DRAM

FEATURES

GENERAL DESCRIPTION

The M12L16161A is 16,777,216 bits synchronous high data

rate Dynamic RAM organized as 2 x 524,288 words by 16 bits,

fabricated with high performance CMOS technology.

Synchronous design allows precise cycle control with the use

of system clock I/O transactions are possible on every clock

cycle. Range of operating frequencies, programmable burst

length and programmable latencies allow the same device to

be useful for a variety of high bandwidth, high performance

memory system applications.

JEDEC standard 3.3V power supply

LVTTL compatible with multiplexed address

Dual banks operation

MRS cycle with address key programs

CAS Latency (2 & 3 )

Burst Length (1, 2, 4, 8 & full page)

Burst Type (Sequential & Interleave)

All inputs are sampled at the positive going edge of the

system clock

Burst Read Single-bit Write operation

DQM for masking

Auto & self refresh

ORDERING INFORMATION

32ms refresh period (2K cycle)

Product ID

Max Freq.

Package

Comments

M12L16161A-5TIG2Q

M12L16161A-7TIG2Q

TSOP(II)

Pb-free

200MHz

143MHz

PIN CONFIGURATION (TOP VIEW)

(TSOPII 50L, 400milX825mil Body, 0.8mm Pin Pitch )

VDD

DQ0

DQ1

VSSQ

DQ2

DQ3

VDDQ

DQ4

DQ5

VSSQ

DQ6

DQ7

VDDQ

LDQM

VSS

DQ15

DQ14

VSSQ

DQ13

DQ12

VDDQ

DQ11

DQ10

VSSQ

DQ9

DQ8

VDDQ

N.C/RFU

UDQM

CLK

CKE

N.C

CAS

RAS

A10/AP

50PIN TSOP(II)

(400mil x 825mil)

(0.8 mm PIN PITCH)

VDD

VSS

Elite Semiconductor Memory Technology Inc.

Publication Date : Feb. 2012

Revision : 1.0 1/28

12 3 4 5 6 7...28

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